From patchwork Mon Jul 4 15:27:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 587560 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADA0FCCA481 for ; Mon, 4 Jul 2022 15:28:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234105AbiGDP2J (ORCPT ); Mon, 4 Jul 2022 11:28:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234182AbiGDP1y (ORCPT ); Mon, 4 Jul 2022 11:27:54 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E402DF1C for ; Mon, 4 Jul 2022 08:27:51 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id y16so16312858lfb.9 for ; Mon, 04 Jul 2022 08:27:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y02pUzaIb4vWAuHWJrfEhGoFcBGtFsnOoH2dr3h2e/c=; b=RADDo9oz2yYxYzwcI+l/XVSnfHGHouq7bPNm4JtM58qS5Zw5Ee/bi2YYEekk3zNlYV 1oNVtQDwSiOeoqgd3FXyuhOBTHbYJ1yeq/1WsJ2cLrlixm/TRfip9SUwS39XOtX/O2QK JCa2TVFDI0kAeajcljJ2YeeCnzhQnDV1YX5XEJZthhEGLwbTxwMw1WjbTveJa2MqT73T xwYOfTcSNroEU3Z9a0C8k8uQMPKmVG6PeOFCaFeCJPREj8tYLlV5EN3K18gswsr9FzI8 sQJ7Mx51mC221Ec9FE9FHorSPSInaTuyaHiRYwHUYbXnhttbyE6pKHRN/v6KRC6whQiV gdUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y02pUzaIb4vWAuHWJrfEhGoFcBGtFsnOoH2dr3h2e/c=; b=reKuriiirYBSFeiTkm/ub5DSb/0MWTFKBKs64XGeFlFHeOTaLrp8c1tTlsLs6ul61R EOFdSdsKYCBQSn8Et+s4eqQWsCOQA/ob6G6lMa11Vzhw6/ysrdmdf2xITaMX5kaUs0Si VtPk1KMORt+2X8bH4eHsLPbGKabZg6t7CUv/ttLYwFXKcuvuUBWnEdz7TGL5sZLRAt59 7v64NQlHnxJecwBSH1AqiDAEZXI2BD5LvlRSW8qoGLFpdavzAQQntY45gD1Rng3pkUfn 8N1RSOfeWEqDN22eL/uwWxwy7Gpzgf1FSTljt1qkDHwpz4Pd2nfIWGVSD6wSGILbXo1o JvlA== X-Gm-Message-State: AJIora+8sIFjaGgSlH0QUH73GZmVpP6eRt0AwAeUIQW7LzFAA+begjgl 9HLXK6xq6FslpnLWRKWY+cHrUw== X-Google-Smtp-Source: AGRyM1sRtunOzOc702ZgyS9egEBzllJSY+uvqPl1hLzS0zf37PJBO8rgG5Kq9FyTwJloeR6NcArNLQ== X-Received: by 2002:a19:650b:0:b0:47f:7dd0:5ec6 with SMTP id z11-20020a19650b000000b0047f7dd05ec6mr18686111lfb.149.1656948469950; Mon, 04 Jul 2022 08:27:49 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h14-20020a056512220e00b004786eb19049sm5175820lfu.24.2022.07.04.08.27.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jul 2022 08:27:49 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Johan Hovold , Rob Herring , Johan Hovold Subject: [PATCH v16 3/6] PCI: dwc: split MSI IRQ parsing/allocation to a separate function Date: Mon, 4 Jul 2022 18:27:43 +0300 Message-Id: <20220704152746.807550-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220704152746.807550-1-dmitry.baryshkov@linaro.org> References: <20220704152746.807550-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Split handling of MSI host IRQs to a separate dw_pcie_msi_host_init() function. The code is complex enough to warrant a separate function. Reviewed-by: Rob Herring Reviewed-by: Johan Hovold Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 101 ++++++++++-------- 1 file changed, 57 insertions(+), 44 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 4c5b3f70ab17..3ba531da99d4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -290,6 +290,61 @@ static void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); } +static int dw_pcie_msi_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + struct platform_device *pdev = to_platform_device(dev); + int ret; + u32 ctrl, num_ctrls; + + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + for (ctrl = 0; ctrl < num_ctrls; ctrl++) + pp->irq_mask[ctrl] = ~0; + + if (!pp->msi_irq[0]) { + int irq = platform_get_irq_byname_optional(pdev, "msi"); + + if (irq < 0) { + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + } + pp->msi_irq[0] = irq; + } + + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + + ret = dw_pcie_allocate_domains(pp); + if (ret) + return ret; + + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { + if (pp->msi_irq[ctrl] > 0) + irq_set_chained_handler_and_data(pp->msi_irq[ctrl], + dw_chained_msi_isr, + pp); + } + + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); + if (ret) + dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); + + pp->msi_page = alloc_page(GFP_DMA32); + pp->msi_data = dma_map_page(pci->dev, pp->msi_page, 0, + PAGE_SIZE, DMA_FROM_DEVICE); + ret = dma_mapping_error(pci->dev, pp->msi_data); + if (ret) { + dev_err(pci->dev, "Failed to map MSI data\n"); + pp->msi_page = NULL; + pp->msi_data = 0; + dw_pcie_free_msi(pp); + return ret; + } + + return 0; +} + int dw_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -367,51 +422,9 @@ int dw_pcie_host_init(struct pcie_port *pp) if (ret < 0) return ret; } else if (pp->has_msi_ctrl) { - u32 ctrl, num_ctrls; - - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - for (ctrl = 0; ctrl < num_ctrls; ctrl++) - pp->irq_mask[ctrl] = ~0; - - if (!pp->msi_irq[0]) { - int irq = platform_get_irq_byname_optional(pdev, "msi"); - - if (irq < 0) { - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - } - pp->msi_irq[0] = irq; - } - - pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; - - ret = dw_pcie_allocate_domains(pp); - if (ret) + ret = dw_pcie_msi_host_init(pp); + if (ret < 0) return ret; - - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { - if (pp->msi_irq[ctrl] > 0) - irq_set_chained_handler_and_data(pp->msi_irq[ctrl], - dw_chained_msi_isr, - pp); - } - - ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); - if (ret) - dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); - - pp->msi_page = alloc_page(GFP_DMA32); - pp->msi_data = dma_map_page(pci->dev, pp->msi_page, 0, - PAGE_SIZE, DMA_FROM_DEVICE); - ret = dma_mapping_error(pci->dev, pp->msi_data); - if (ret) { - dev_err(pci->dev, "Failed to map MSI data\n"); - __free_page(pp->msi_page); - pp->msi_page = NULL; - pp->msi_data = 0; - goto err_free_msi; - } } }