From patchwork Wed Jun 8 10:52:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B3C7CCA47B for ; Wed, 8 Jun 2022 10:52:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236884AbiFHKwr (ORCPT ); Wed, 8 Jun 2022 06:52:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237074AbiFHKwp (ORCPT ); Wed, 8 Jun 2022 06:52:45 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7E9B10F379 for ; Wed, 8 Jun 2022 03:52:42 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id be31so32632399lfb.10 for ; Wed, 08 Jun 2022 03:52:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/EDLNTI5pI/Mi1iA33N6km0sR5Uc9crbW1Xns2oX9B0=; b=ZpgLy3347N6xmgc9u3MB4Uet9lJZG13t7Q8l9yDLDSIKyRG5tGvbb/6GQc2WSvkDe6 Mdn7yfcF87ujDdIx6E+f+ELWLEk73yYvcxku10ulwAiwfm7aUMi3cgrH/KTPAzAg4O8I Soofsei5CS582uSVjmBOSes8fQdRDwZa8rS2njoLed1tSMRubT8sY7U1wspEqIG8Kben Y7sAPu6uDalLJ24j2h7zqI5YWHKY4e1Ti6pmfhyzmo6SR1xNDFA4HOYziCXAVwqfsegQ 5NOL4R0+QRmWN0qweKn932DXSTJXfGy47WmqS+DZE4WojqMkSMDhucmVKE27OXzP6Sw/ Xahw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/EDLNTI5pI/Mi1iA33N6km0sR5Uc9crbW1Xns2oX9B0=; b=BbfOB9pFh7mEkPOl0K8OgyewGArfxWJ+lM2lTmtY+3oGOlRPTIq9UFAeymBh9L3ycd T8IagUVM8drmLLabZl45IAraKdEHXxrpQ41fIa9jmTdRhPL4w6rWfpOgv+7ddwbDoqOf bKV2RaoIGwQKF8bGbGGScN9omODrBEd9D4zT1GZPLL67yD7qSgZ2pZf2L7AnM0FMueFm XkfCHBYySFegNH5Q3FMLC+bXL+qwMkF741FgOBfQtR5lPMFdpsLLXuj5YjWIy8spUrTC 1YCtCGwwTobwyszQSYiAaJJYeLOs43A25JeGUucxMBKJMESJ1OcveivfHIXTD7D3zwfi y4kw== X-Gm-Message-State: AOAM533WqgA0QdS2H/YVDZKdV1VkhGLMYT3N8QkMxxIUr+mQiUuNf8c2 RYO/QR0KV4eMy1saQ3T9na0Qdw== X-Google-Smtp-Source: ABdhPJwk6LnQOmbzcyD5V2RuZVFVjWQh24vK3RUTWBaBSTp9o18iKdozrkezy9JNLv/yt2vxxnf1xA== X-Received: by 2002:a05:6512:703:b0:479:157a:c18d with SMTP id b3-20020a056512070300b00479157ac18dmr18372154lfs.639.1654685561325; Wed, 08 Jun 2022 03:52:41 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id e9-20020a2e5009000000b002556b0cd5acsm3232337ljb.56.2022.06.08.03.52.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 03:52:40 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas Cc: Johan Hovold , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pci@vger.kernel.org, Johan Hovold Subject: [PATCH v11 2/5] clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks Date: Wed, 8 Jun 2022 13:52:35 +0300 Message-Id: <20220608105238.2973600-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608105238.2973600-1-dmitry.baryshkov@linaro.org> References: <20220608105238.2973600-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let the clock framework automatically park the clock when the clock is switched off and restore the parent when the clock is switched on. Reviewed-by: Johan Hovold Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd --- drivers/clk/qcom/gcc-sm8450.c | 49 ++++++++++------------------------- 1 file changed, 13 insertions(+), 36 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index 593a195467ff..666efa5ff978 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -17,6 +17,7 @@ #include "clk-regmap.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" #include "gdsc.h" #include "reset.h" @@ -26,9 +27,7 @@ enum { P_GCC_GPLL0_OUT_MAIN, P_GCC_GPLL4_OUT_MAIN, P_GCC_GPLL9_OUT_MAIN, - P_PCIE_0_PIPE_CLK, P_PCIE_1_PHY_AUX_CLK, - P_PCIE_1_PIPE_CLK, P_SLEEP_CLK, P_UFS_PHY_RX_SYMBOL_0_CLK, P_UFS_PHY_RX_SYMBOL_1_CLK, @@ -153,16 +152,6 @@ static const struct clk_parent_data gcc_parent_data_3[] = { { .fw_name = "bi_tcxo" }, }; -static const struct parent_map gcc_parent_map_4[] = { - { P_PCIE_0_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_4[] = { - { .fw_name = "pcie_0_pipe_clk", }, - { .fw_name = "bi_tcxo", }, -}; - static const struct parent_map gcc_parent_map_5[] = { { P_PCIE_1_PHY_AUX_CLK, 0 }, { P_BI_TCXO, 2 }, @@ -173,16 +162,6 @@ static const struct clk_parent_data gcc_parent_data_5[] = { { .fw_name = "bi_tcxo" }, }; -static const struct parent_map gcc_parent_map_6[] = { - { P_PCIE_1_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_6[] = { - { .fw_name = "pcie_1_pipe_clk" }, - { .fw_name = "bi_tcxo" }, -}; - static const struct parent_map gcc_parent_map_7[] = { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, @@ -239,17 +218,16 @@ static const struct clk_parent_data gcc_parent_data_11[] = { { .fw_name = "bi_tcxo" }, }; -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { .reg = 0x7b060, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_4, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk_src", - .parent_data = gcc_parent_data_4, - .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_0_pipe_clk", + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, }; @@ -269,17 +247,16 @@ static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { }, }; -static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { .reg = 0x9d064, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_6, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk_src", - .parent_data = gcc_parent_data_6, - .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_1_pipe_clk", + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, };