| Message ID | 20220513234518.3068480-6-dmitry.baryshkov@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: qcom: initial Inforce IFC6560 board support | expand |
On 2022-05-14 02:45:15, Dmitry Baryshkov wrote: > Add DT entries for the second DWC3 USB host, which is limited to the > USB2.0 (HighSpeed), and the corresponding QUSB PHY. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Some minor style nits below. > --- > arch/arm64/boot/dts/qcom/sdm630.dtsi | 55 ++++++++++++++++++++++++++++ > 1 file changed, 55 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi > index cca56f2fad96..17a1877587cf 100644 > --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi > @@ -1270,6 +1270,20 @@ qusb2phy: phy@c012000 { > status = "disabled"; > }; > > + qusb2phy1: phy@c014000 { Should we rename qusb2phy to qusb2phy0? > + compatible = "qcom,sdm660-qusb2-phy"; > + reg = <0x0c014000 0x180>; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, > + <&gcc GCC_RX1_USB2_CLKREF_CLK>; Should use the correct indentation from the get-go? > + clock-names = "cfg_ahb", "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; > + nvmem-cells = <&qusb2_hstx_trim>; > + status = "disabled"; > + }; > + > sdhc_2: sdhci@c084000 { > compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; > reg = <0x0c084000 0x1000>; > @@ -1375,6 +1389,47 @@ opp-384000000 { > }; > }; > > + usb2: usb@c2f8800 { > + compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; > + reg = <0x0c2f8800 0x400>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, > + <&gcc GCC_USB20_MASTER_CLK>, > + <&gcc GCC_USB20_MOCK_UTMI_CLK>, > + <&gcc GCC_USB20_SLEEP_CLK>; > + clock-names = "cfg_noc", "core", > + "mock_utmi", "sleep"; This fits on one line and stays at 79 characters. - Marijn > + > + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, > + <&gcc GCC_USB20_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <60000000>; > + > + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hs_phy_irq"; > + > + qcom,select-utmi-as-pipe-clk; > + > + resets = <&gcc GCC_USB_20_BCR>; > + > + usb2_dwc3: usb@c200000 { > + compatible = "snps,dwc3"; > + reg = <0x0c200000 0xc8d0>; > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + > + /* This is the HS-only host */ > + maximum-speed = "high-speed"; > + phys = <&qusb2phy1>; > + phy-names = "usb2-phy"; > + snps,hird-threshold = /bits/ 8 <0>; > + }; > + }; > + > mmcc: clock-controller@c8c0000 { > compatible = "qcom,mmcc-sdm630"; > reg = <0x0c8c0000 0x40000>; > -- > 2.35.1 >
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index cca56f2fad96..17a1877587cf 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1270,6 +1270,20 @@ qusb2phy: phy@c012000 { status = "disabled"; }; + qusb2phy1: phy@c014000 { + compatible = "qcom,sdm660-qusb2-phy"; + reg = <0x0c014000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX1_USB2_CLKREF_CLK>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + status = "disabled"; + }; + sdhc_2: sdhci@c084000 { compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0c084000 0x1000>; @@ -1375,6 +1389,47 @@ opp-384000000 { }; }; + usb2: usb@c2f8800 { + compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; + reg = <0x0c2f8800 0x400>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>; + clock-names = "cfg_noc", "core", + "mock_utmi", "sleep"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <60000000>; + + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq"; + + qcom,select-utmi-as-pipe-clk; + + resets = <&gcc GCC_USB_20_BCR>; + + usb2_dwc3: usb@c200000 { + compatible = "snps,dwc3"; + reg = <0x0c200000 0xc8d0>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + /* This is the HS-only host */ + maximum-speed = "high-speed"; + phys = <&qusb2phy1>; + phy-names = "usb2-phy"; + snps,hird-threshold = /bits/ 8 <0>; + }; + }; + mmcc: clock-controller@c8c0000 { compatible = "qcom,mmcc-sdm630"; reg = <0x0c8c0000 0x40000>;
Add DT entries for the second DWC3 USB host, which is limited to the USB2.0 (HighSpeed), and the corresponding QUSB PHY. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 55 ++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+)