From patchwork Fri May 13 13:16:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572596 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F18CC433FE for ; Fri, 13 May 2022 13:17:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1380653AbiEMNRO (ORCPT ); Fri, 13 May 2022 09:17:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380646AbiEMNRI (ORCPT ); Fri, 13 May 2022 09:17:08 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45F3BBE34 for ; Fri, 13 May 2022 06:17:07 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id c24so4994144lfv.11 for ; Fri, 13 May 2022 06:17:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HYUuQ4fR4SBZdSuM6IAnUnoggotKrAQZZIhO70s2q7Y=; b=ChLKujV6Y1lpp9wTj0B3X09dHIg98LpZaep9jTg3LQtxQpL6jRoxuAiHbAzkzvK+nW WMC7hJ2L3f58eWDlyy2nUqUxvDlFmUU+cWTPjLLq7i0J2V5SLdKCJ6HE3Etc686cWMub wqqVXDM+Lxs9tXcthxX/BNsnREsb/MlRM7PplN2/R5WODUupmFUiAHdm99LCdNclHj0R 53xru/fLmBTsbteV9gzgi9qVb2IWDXxs220RJGqgS01IWqm1czhFAjGMqPeLjngF+mjS Uz6J/0BboeLrjmB0OF1BPpyitN3+D7JQc0UPe82uB6OwYCKhafaPHXw/nShrEYpiZhl6 E+mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HYUuQ4fR4SBZdSuM6IAnUnoggotKrAQZZIhO70s2q7Y=; b=5J3arDRwuis28dhxnixOcogTziaUeEQ139mVY1BVAszr5mQQnjvXvvr9dnRnkRldsi dK9zyfmrEEVAeENBvd2hvEu49Gh/yITiY1yZrPht06g+ElAHKbjXxGder2NGGaQMVelF ndPLGdIFzttYUbt2EOlPFPmCPXicSPR1wglf2Edt7Ki05giRc8tSER86Zd0gCglRHHKi mY6bw+o7T96bHOb7fs7iaOKTim+6c9BQ9VyAJhFfh0CMfFQFlSrf33wXheJPC5fhW6XB /26aczQKIK4cMXWpQXT6XNvHuTOX/BqxE4zsjM71abUffnAKo30FwaegYkPZ2O2IMgaE Vkag== X-Gm-Message-State: AOAM532+9ZsBNEdTgo1XLJSuTuQSkrxJHA4gVxKXtAlY26R1oHSNcQHC 5VLOrN7r9qWKtPkEDVkYPqjwAg== X-Google-Smtp-Source: ABdhPJwFJZVeVw2xJQ23xQ/LC7+pFuF2yAN9SdSJFS/y6pRRklPJtslvhOx3xLOhKmUfq5JRSzrejg== X-Received: by 2002:a05:6512:c28:b0:473:b6ce:96fe with SMTP id z40-20020a0565120c2800b00473b6ce96femr3390096lfu.595.1652447825444; Fri, 13 May 2022 06:17:05 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id u22-20020a2ea176000000b0024f3d1dae8fsm436991ljl.23.2022.05.13.06.17.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 06:17:04 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam , Johan Hovold Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v9 09/10] dt-bindings: PCI: qcom: Support additional MSI interrupts Date: Fri, 13 May 2022 16:16:54 +0300 Message-Id: <20220513131655.2927616-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513131655.2927616-1-dmitry.baryshkov@linaro.org> References: <20220513131655.2927616-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Document mapping of additional interrupts. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/pci/qcom,pcie.yaml | 53 +++++++++++++++++-- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 0b69b12b849e..fe8f9a62a665 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -43,11 +43,12 @@ properties: maxItems: 5 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 8 interrupt-names: - items: - - const: msi + minItems: 1 + maxItems: 8 # Common definitions for clocks, clock-names and reset. # Platform constraints are described later. @@ -623,6 +624,52 @@ allOf: - resets - reset-names + # On newer chipsets support either 1 or 8 msi interrupts + # On older chipsets it's always 1 msi interrupt + - if: + properties: + compatibles: + contains: + enum: + - qcom,pcie-msm8996 + - qcom,pcie-sc7280 + - qcom,pcie-sc8180x + - qcom,pcie-sdm845 + - qcom,pcie-sm8150 + - qcom,pcie-sm8250 + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + then: + oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + maxItems: 1 + items: + - const: msi + - properties: + interrupts: + minItems: 8 + interrupt-names: + minItems: 8 + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + unevaluatedProperties: false examples: