From patchwork Sun May 8 10:48:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 571297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A339FC43219 for ; Sun, 8 May 2022 10:49:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231758AbiEHKxD (ORCPT ); Sun, 8 May 2022 06:53:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231610AbiEHKw5 (ORCPT ); Sun, 8 May 2022 06:52:57 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7F92DEE3; Sun, 8 May 2022 03:49:07 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id gh6so21929369ejb.0; Sun, 08 May 2022 03:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jRvjrwoDTG2vGn1+XsgjmHuelkhoFakkhEz4+edI7ZE=; b=Qap5WEO7IaF080iuoxxkrpgNLpgEgiF9PhIpfdOyCRkKd0qMoJtiNc9DyVToQ0FNYS hz+gEay8DGfmqmG8dMexZswzr+FPWUGeLSvZwp0bqnJ7bPr5ztUFeuwOrROoLCyxGptV kOksvV1NacDXm36CfZxzKcGO6RZrnl+NqxtNhaysWRj5JM6RL01ENXdPFOyf5MqStd3p h+iHNEpcSrPfo4eeE+BAMY7rAZM91D2n5g78WX2+Q8kRqa1nOhwD9QaR4Iu27/RTnmBP MI3Ytn999waSZ92nMW2nlfKsj/BvaN8oDV95tjqfxm/q+E+grVh0vW3V0DWQokmXEG9M PDyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jRvjrwoDTG2vGn1+XsgjmHuelkhoFakkhEz4+edI7ZE=; b=UlsmVnQcHCzr8RHLcNmwNqEFtzFbXRQ7EiHg02j/Kdd94j/rNQdf7j+SxMsHSs0EyV zDsxk+mJ0lVQvYVLIFCxSNgJusiYb85TPe/8DXXVy4tKvSaD7tXQFA3HEPA1u6LBEb/e j8+O49Ki0pG3Czle6deMRMRiMFpKVXSPHg68m8z0il6xOki7M0pLqnCQaCdF/3lDzsIh SDpT3zQ7UERMsPtM0VBvFjIMYga78yYHAMLNq6UexfPCTAgsifJnHMdYBLfm+YC12VKs lm6C8+CNxtVbJeWR5MQ7+fTqjh7boRmHB6B8WIgipl+ED6+sRP+jTbj8R7OUb+7bDfxp NvAA== X-Gm-Message-State: AOAM533aR8/xsMy212d0JdD4RARuXB9OLwQXGy3cboEItHqItCQD43fa +ohAmSXxJyZ+/rbT8lZIMMjZT8twe8fDMg== X-Google-Smtp-Source: ABdhPJxklFBtaaBdJ1PDtdKt/h7+g9cXSipxIzeW3Vr2CBrluL7R1Wzr7l5XdcXtL+EnJ0gBbV65Sg== X-Received: by 2002:a17:906:2294:b0:6f3:bd02:95a3 with SMTP id p20-20020a170906229400b006f3bd0295a3mr10244746eja.201.1652006947279; Sun, 08 May 2022 03:49:07 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id hg12-20020a1709072ccc00b006f3ef214e0csm3917471ejc.114.2022.05.08.03.49.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 May 2022 03:49:06 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v3 06/11] clk: qcom: ipq8074: set BRANCH_HALT_DELAY flag for UBI clocks Date: Sun, 8 May 2022 12:48:50 +0200 Message-Id: <20220508104855.78804-6-robimarko@gmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220508104855.78804-1-robimarko@gmail.com> References: <20220508104855.78804-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Currently, attempting to enable the UBI clocks will cause the stuck at off warning to be printed and clk_enable will fail. [ 14.936694] gcc_ubi1_ahb_clk status stuck at 'off' Downstream 5.4 QCA kernel has fixed this by seting the BRANCH_HALT_DELAY flag on UBI clocks, so lets do the same. Fixes: 5736294aef83 ("clk: qcom: ipq8074: add NSS clocks") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index c964e43ba68a..85076c1383c7 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -3372,6 +3372,7 @@ static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = { static struct clk_branch gcc_ubi0_ahb_clk = { .halt_reg = 0x6820c, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x6820c, .enable_mask = BIT(0), @@ -3389,6 +3390,7 @@ static struct clk_branch gcc_ubi0_ahb_clk = { static struct clk_branch gcc_ubi0_axi_clk = { .halt_reg = 0x68200, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68200, .enable_mask = BIT(0), @@ -3406,6 +3408,7 @@ static struct clk_branch gcc_ubi0_axi_clk = { static struct clk_branch gcc_ubi0_nc_axi_clk = { .halt_reg = 0x68204, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68204, .enable_mask = BIT(0), @@ -3423,6 +3426,7 @@ static struct clk_branch gcc_ubi0_nc_axi_clk = { static struct clk_branch gcc_ubi0_core_clk = { .halt_reg = 0x68210, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68210, .enable_mask = BIT(0), @@ -3440,6 +3444,7 @@ static struct clk_branch gcc_ubi0_core_clk = { static struct clk_branch gcc_ubi0_mpt_clk = { .halt_reg = 0x68208, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68208, .enable_mask = BIT(0), @@ -3457,6 +3462,7 @@ static struct clk_branch gcc_ubi0_mpt_clk = { static struct clk_branch gcc_ubi1_ahb_clk = { .halt_reg = 0x6822c, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x6822c, .enable_mask = BIT(0), @@ -3474,6 +3480,7 @@ static struct clk_branch gcc_ubi1_ahb_clk = { static struct clk_branch gcc_ubi1_axi_clk = { .halt_reg = 0x68220, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68220, .enable_mask = BIT(0), @@ -3491,6 +3498,7 @@ static struct clk_branch gcc_ubi1_axi_clk = { static struct clk_branch gcc_ubi1_nc_axi_clk = { .halt_reg = 0x68224, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68224, .enable_mask = BIT(0), @@ -3508,6 +3516,7 @@ static struct clk_branch gcc_ubi1_nc_axi_clk = { static struct clk_branch gcc_ubi1_core_clk = { .halt_reg = 0x68230, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68230, .enable_mask = BIT(0), @@ -3525,6 +3534,7 @@ static struct clk_branch gcc_ubi1_core_clk = { static struct clk_branch gcc_ubi1_mpt_clk = { .halt_reg = 0x68228, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68228, .enable_mask = BIT(0),