From patchwork Sun May 1 19:21:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 568587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 683F2C4332F for ; Sun, 1 May 2022 19:22:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353489AbiEATZ2 (ORCPT ); Sun, 1 May 2022 15:25:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352300AbiEATZW (ORCPT ); Sun, 1 May 2022 15:25:22 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BF46B1F9 for ; Sun, 1 May 2022 12:21:55 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id w19so22186015lfu.11 for ; Sun, 01 May 2022 12:21:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EyEhF7k2pEreaYiBT9N8RZXij7PCGcC1qIj0oDB7VuY=; b=orZ1ch6O8YxVgW+lGRdQvK3l94rbdGhRsjYcVq1SD3hjvHRMDTT927ELMHh5jL4F3Z kzxjwsq0x8rq1isgnTPGw8eUhZEv4njcjMihdoXCULOFlVJfCYnbZPHo3Anath4RqqO5 KnkCSMYSGAQksz4gUg478chqlVzn1d14i5nHjQTX/1RYPD7bPeoVHwyvX4mCfVs1WeK7 Secfs/tewcptRc5regmPNTMuzVvaiiws2N688AHq0MEHNkcqlJcBS73dk+CUb/cIMOIJ yM+CNfwp7VesWNBo/ed6zg4GwD6AlZ+oNW8qZxcfDFWvlctu401EcfrctQPRgHAC0IjJ r+TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EyEhF7k2pEreaYiBT9N8RZXij7PCGcC1qIj0oDB7VuY=; b=0S/xGL7+7KxrMiUY8pESp/uoqp3rNwESbPCbwHhKivGmlPc+IlrlF6yaMO5PnSUIvU cmjrNd5dtEpCkZteuPTnT6NCtS687b24Y+Gm9RwNfIAHge9h3d0i53liLKHCuAHlhslk sHH35qLJKwVl9xqJ8lFo5GueFIpeAZ0mzof97vnO1MmF04A/XEgi1gOsHlyeblFQW/Ky CjE57rqaVdmmLHwnZuv6TDe1nrIhrHfmQO5820oL7sKui0JSZY1L1xMQ7WNSqtcpnnOs vTyceatajuO9wByBIYkHRdyrAaC751+TYzoym9ZbRy32cF9AN3R375j8yxfSh+e3dY6s nfbA== X-Gm-Message-State: AOAM5322lWKqWcWacQ+qC5V8vw7wSwYRURYkOPHbIDmvTxG/zSiBhdJC qcCP1IhfJFGjc+x51xYfBksI4g== X-Google-Smtp-Source: ABdhPJxGkltc7I3qBt2CB+HOmaEl/OwnQRC0EHZ3w7RgFM0PMp9wdGeB3xmCLkit25rDG0nu1dWW5A== X-Received: by 2002:a05:6512:203b:b0:472:4d8b:b124 with SMTP id s27-20020a056512203b00b004724d8bb124mr7137366lfs.241.1651432913516; Sun, 01 May 2022 12:21:53 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id q3-20020a2e8743000000b0024f3d1daee6sm865928ljj.110.2022.05.01.12.21.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 12:21:53 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas Cc: Prasad Malisetty , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v4 3/5] clk: qcom: gcc-sm8450: use new clk_regmap_pipe_ops for PCIe pipe clocks Date: Sun, 1 May 2022 22:21:47 +0300 Message-Id: <20220501192149.4128158-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220501192149.4128158-1-dmitry.baryshkov@linaro.org> References: <20220501192149.4128158-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use newly defined clk_regmap_pipe_ops for PCIe pipe clocks to let the clock framework automatically park the clock when the clock is switched off and restore the parent when the clock is switched on. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-sm8450.c | 51 +++++++++++++---------------------- 1 file changed, 19 insertions(+), 32 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index 593a195467ff..4dd48d62c2ff 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -17,6 +17,7 @@ #include "clk-regmap.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +#include "clk-regmap-pipe.h" #include "gdsc.h" #include "reset.h" @@ -26,9 +27,7 @@ enum { P_GCC_GPLL0_OUT_MAIN, P_GCC_GPLL4_OUT_MAIN, P_GCC_GPLL9_OUT_MAIN, - P_PCIE_0_PIPE_CLK, P_PCIE_1_PHY_AUX_CLK, - P_PCIE_1_PIPE_CLK, P_SLEEP_CLK, P_UFS_PHY_RX_SYMBOL_0_CLK, P_UFS_PHY_RX_SYMBOL_1_CLK, @@ -153,16 +152,6 @@ static const struct clk_parent_data gcc_parent_data_3[] = { { .fw_name = "bi_tcxo" }, }; -static const struct parent_map gcc_parent_map_4[] = { - { P_PCIE_0_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_4[] = { - { .fw_name = "pcie_0_pipe_clk", }, - { .fw_name = "bi_tcxo", }, -}; - static const struct parent_map gcc_parent_map_5[] = { { P_PCIE_1_PHY_AUX_CLK, 0 }, { P_BI_TCXO, 2 }, @@ -173,16 +162,6 @@ static const struct clk_parent_data gcc_parent_data_5[] = { { .fw_name = "bi_tcxo" }, }; -static const struct parent_map gcc_parent_map_6[] = { - { P_PCIE_1_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_6[] = { - { .fw_name = "pcie_1_pipe_clk" }, - { .fw_name = "bi_tcxo" }, -}; - static const struct parent_map gcc_parent_map_7[] = { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, @@ -239,17 +218,21 @@ static const struct clk_parent_data gcc_parent_data_11[] = { { .fw_name = "bi_tcxo" }, }; -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { +static struct clk_regmap_pipe gcc_pcie_0_pipe_clk_src = { .reg = 0x7b060, .shift = 0, .width = 2, - .parent_map = gcc_parent_map_4, + .enable_val = 0, /* pipe_clk */ + .disable_val = 2, /* bi_tcxo */ .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk_src", - .parent_data = gcc_parent_data_4, - .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_0_pipe_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_pipe_ops, }, }, }; @@ -269,17 +252,21 @@ static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { }, }; -static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { +static struct clk_regmap_pipe gcc_pcie_1_pipe_clk_src = { .reg = 0x9d064, .shift = 0, .width = 2, - .parent_map = gcc_parent_map_6, + .enable_val = 0, /* pipe_clk */ + .disable_val = 2, /* bi_tcxo */ .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk_src", - .parent_data = gcc_parent_data_6, - .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_1_pipe_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_pipe_ops, }, }, };