From patchwork Fri Apr 29 21:42:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 568212 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 598FEC433F5 for ; Fri, 29 Apr 2022 21:43:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238689AbiD2VqS (ORCPT ); Fri, 29 Apr 2022 17:46:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238676AbiD2VqR (ORCPT ); Fri, 29 Apr 2022 17:46:17 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E2D579397 for ; Fri, 29 Apr 2022 14:42:56 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id bu29so16302395lfb.0 for ; Fri, 29 Apr 2022 14:42:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ncVhMJxrohn0+P1cFmOcnIFJEP0t7Z52SvJtNUy/BIs=; b=kSx8B5MYfuey4jDbsS/+ZnbpWUK2aYadezjOYORGZO7ZMCnbSzJEx+qjmYl4jCkBTP NgcQUoKQh8FUG1ZLnHV6dJM1decZ/GZ9SH76nDJY+TW9r+Qej48E5wXQKcLuRz3c0MxF 9Mf1YmC2uEoNbARiCHawAfNQmyyyfRelRQrjAprm+w5yg1UpUL+PkFRGKOnAMpIPEsGw H2gXXniOUJ3bb7sQfc/7Am/RExBpGuyPDp7ZPG5mYxNMV/T+vnKdjjh51PaUVTGrXEOz plx9CPa+pufDSZd+YBIgHSPbbks5NO2WSl4+h5kOBzNI/jMLKbO7xX1pESblv73aJdEW 27sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ncVhMJxrohn0+P1cFmOcnIFJEP0t7Z52SvJtNUy/BIs=; b=eblt6PotP2R+uFXf6pRRK0Ni3pwp17i2QQ2Xl7rvUIXa194oX5zM28gjib88DdoibQ HC6KSTujrgL4+l/hAB8RjdJmWTtpONzTnD1YImnv5ZOcOBBBDOBFkwa8H6hwVylB9wIe X5sL9whvqHFjl8VjNYRedqPfIYuUHnAELAwDiHHDXmNAO7FWy2qQ56UYhosqKKKg1hXh l+goEYtmlP+PncY3kNOsEpxNs2zG44JE6zEd7MQJx4c/l7vaSqKA3oIgeeDuvGFX99vW iUhwyW6qIizlbc4AFRC3QvPj4t9Z39r6r4471RUrMNpWiwJ+7AERFHRSowW7lxB6hIwu JrOg== X-Gm-Message-State: AOAM532ju5PFwiABDhLzxeMbl+jYlFZmmUrcQCcfYNf/R4Xr1zRAD8Ri E7JK2ASmOznZkSa4vCAvBG4jLg== X-Google-Smtp-Source: ABdhPJzkBzz2G5DWzhONhXDruSg7+Bk4LQdmYe9bzBfn6j9UQ2ibE3/hmIHstMCJACe4hozziai3YA== X-Received: by 2002:ac2:4ac9:0:b0:471:f6da:640d with SMTP id m9-20020ac24ac9000000b00471f6da640dmr900074lfp.286.1651268574342; Fri, 29 Apr 2022 14:42:54 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g4-20020a19ac04000000b0047255d211f6sm30520lfc.293.2022.04.29.14.42.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 14:42:54 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 4/7] PCI: dwc: Export several functions useful for MSI implentations Date: Sat, 30 Apr 2022 00:42:47 +0300 Message-Id: <20220429214250.3728510-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429214250.3728510-1-dmitry.baryshkov@linaro.org> References: <20220429214250.3728510-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Supporting multiple MSI interrupts on Qualcomm hardware would benefit from having these functions being exported rather than static. Note that both designware and qcom driver can not be built as modules, so no need to use EXPORT_SYMBOL here. Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 62 ++++++++++++------- drivers/pci/controller/dwc/pcie-designware.h | 11 ++++ 2 files changed, 49 insertions(+), 24 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 92dcaeabe2bf..c3b8ab278a00 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -255,7 +255,39 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) return 0; } -static void dw_pcie_free_msi(struct pcie_port *pp) +int dw_pcie_allocate_msi(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + int ret; + + ret = dw_pcie_allocate_domains(pp); + if (ret) + return ret; + + if (pp->msi_irq > 0) + irq_set_chained_handler_and_data(pp->msi_irq, + dw_chained_msi_isr, + pp); + + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); + if (ret) + dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); + + pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, + sizeof(pp->msi_msg), + DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC); + ret = dma_mapping_error(pci->dev, pp->msi_data); + if (ret) { + dev_err(pci->dev, "Failed to map MSI data\n"); + pp->msi_data = 0; + return ret; + } + + return 0; +} + +void dw_pcie_free_msi(struct pcie_port *pp) { if (pp->msi_irq > 0) irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL); @@ -357,6 +389,9 @@ int dw_pcie_host_init(struct pcie_port *pp) return -EINVAL; } + /* this can be overridden by msi_host_init() if necessary */ + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + if (pp->ops->msi_host_init) { ret = pp->ops->msi_host_init(pp); if (ret < 0) @@ -377,30 +412,9 @@ int dw_pcie_host_init(struct pcie_port *pp) } } - pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; - - ret = dw_pcie_allocate_domains(pp); - if (ret) + ret = dw_pcie_allocate_msi(pp); + if (ret < 0) return ret; - - if (pp->msi_irq > 0) - irq_set_chained_handler_and_data(pp->msi_irq, - dw_chained_msi_isr, - pp); - - ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); - if (ret) - dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); - - pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, - sizeof(pp->msi_msg), - DMA_FROM_DEVICE, - DMA_ATTR_SKIP_CPU_SYNC); - if (dma_mapping_error(pci->dev, pp->msi_data)) { - dev_err(pci->dev, "Failed to map MSI data\n"); - pp->msi_data = 0; - goto err_free_msi; - } } } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index e1c48b71e0d2..f72447f15dc5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -374,6 +374,8 @@ void dw_pcie_host_deinit(struct pcie_port *pp); int dw_pcie_allocate_domains(struct pcie_port *pp); void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where); +int dw_pcie_allocate_msi(struct pcie_port *pp); +void dw_pcie_free_msi(struct pcie_port *pp); #else static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) { @@ -403,6 +405,15 @@ static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, { return NULL; } + +static int dw_pcie_allocate_msi(struct pcie_port *pp) +{ + return -EINVAL; +} + +static void dw_pcie_free_msi(struct pcie_port *pp) +{ +} #endif #ifdef CONFIG_PCIE_DW_EP