From patchwork Thu Apr 28 11:59:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 567226 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36EACC4167E for ; Thu, 28 Apr 2022 11:59:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345980AbiD1MC5 (ORCPT ); Thu, 28 Apr 2022 08:02:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345826AbiD1MCz (ORCPT ); Thu, 28 Apr 2022 08:02:55 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D0A689325 for ; Thu, 28 Apr 2022 04:59:40 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id w1so8194406lfa.4 for ; Thu, 28 Apr 2022 04:59:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ncVhMJxrohn0+P1cFmOcnIFJEP0t7Z52SvJtNUy/BIs=; b=aqrRcw9/JLhQ5Tsuscpt3XxutIqrmcVUNuK4fw8MPf9CveUSx94iVeN1z1g4AzUN5N 3CcRsjDEDvwmDs624gFW0dtEcdYrJGPR3FtpxdoC5wVGYVGt8ffsjVl+EdSv16GBsr9Z A+215m3oGxGitrR/FwLUZ6uLzQwY9rynk36s5e7VlFDtjzJAVI51u5BnkT4sDmmffHg0 IEG4vur12J84EUqlDrv5KxF5QZ6ZA9SJZ8rhFB4mmHGI4YXITwIxJlvIqRK0iW8+uK4W FhEVsHytJ/GIYaJMsaLDC2qSG9PDD3wT0ME4v0tafCewBdzyKnUBGfqdGleVVFSPm8xD kf3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ncVhMJxrohn0+P1cFmOcnIFJEP0t7Z52SvJtNUy/BIs=; b=NE3DO0/EGLVIEHXh8mi3gN3FpKm79EdzsSZi+sjh+61z7PblmXV9UAu6xRbnVXbNg4 mENq80ePREvRk8Fn/6xVjDZPdC86R2X5ZRb+Tuqh4LnqqwmT+NJpH5dD+02fXBxGapjF W01Poaa5ulbrgbTMzsM+MfGF9RcdyfLWagCK0KUNwX/SN32ToIxYt73C+HJ/9sz/S4GM 9bJQjVWT27x2AXmZYJY3PGEhEhg1xttxtl5oVXKy+HdeMgnqsNqfWN1sbi581G+E9Qjv zsZqVJeVUFpvzdatUyGQQZqSoSdXtBeRF/L1QqfhFILp82njyOk0kzS8hpTf+Stc6FZ6 nGvA== X-Gm-Message-State: AOAM533O+cuCXWVzXnxdQliGx+4CWS9TLCMR0TKwqqXPLZ9UIYU1TnoC RHl57fz8Vg5X186DwrpEeTeE6A== X-Google-Smtp-Source: ABdhPJxDSwC47P6a0bMaxmtOFLMd+qlcG2Qu8HzSGMxiYw4GKzis1BZ1f38aYyZY3PVIq8/u5HjbPw== X-Received: by 2002:a05:6512:2255:b0:471:910e:66ba with SMTP id i21-20020a056512225500b00471910e66bamr23633378lfu.290.1651147178888; Thu, 28 Apr 2022 04:59:38 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id f1-20020a2e1f01000000b0024602522b5dsm2069137ljf.120.2022.04.28.04.59.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Apr 2022 04:59:38 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 4/7] PCI: dwc: Export several functions useful for MSI implentations Date: Thu, 28 Apr 2022 14:59:31 +0300 Message-Id: <20220428115934.3414641-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220428115934.3414641-1-dmitry.baryshkov@linaro.org> References: <20220428115934.3414641-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Supporting multiple MSI interrupts on Qualcomm hardware would benefit from having these functions being exported rather than static. Note that both designware and qcom driver can not be built as modules, so no need to use EXPORT_SYMBOL here. Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 62 ++++++++++++------- drivers/pci/controller/dwc/pcie-designware.h | 11 ++++ 2 files changed, 49 insertions(+), 24 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 92dcaeabe2bf..c3b8ab278a00 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -255,7 +255,39 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) return 0; } -static void dw_pcie_free_msi(struct pcie_port *pp) +int dw_pcie_allocate_msi(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + int ret; + + ret = dw_pcie_allocate_domains(pp); + if (ret) + return ret; + + if (pp->msi_irq > 0) + irq_set_chained_handler_and_data(pp->msi_irq, + dw_chained_msi_isr, + pp); + + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); + if (ret) + dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); + + pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, + sizeof(pp->msi_msg), + DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC); + ret = dma_mapping_error(pci->dev, pp->msi_data); + if (ret) { + dev_err(pci->dev, "Failed to map MSI data\n"); + pp->msi_data = 0; + return ret; + } + + return 0; +} + +void dw_pcie_free_msi(struct pcie_port *pp) { if (pp->msi_irq > 0) irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL); @@ -357,6 +389,9 @@ int dw_pcie_host_init(struct pcie_port *pp) return -EINVAL; } + /* this can be overridden by msi_host_init() if necessary */ + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + if (pp->ops->msi_host_init) { ret = pp->ops->msi_host_init(pp); if (ret < 0) @@ -377,30 +412,9 @@ int dw_pcie_host_init(struct pcie_port *pp) } } - pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; - - ret = dw_pcie_allocate_domains(pp); - if (ret) + ret = dw_pcie_allocate_msi(pp); + if (ret < 0) return ret; - - if (pp->msi_irq > 0) - irq_set_chained_handler_and_data(pp->msi_irq, - dw_chained_msi_isr, - pp); - - ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); - if (ret) - dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); - - pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, - sizeof(pp->msi_msg), - DMA_FROM_DEVICE, - DMA_ATTR_SKIP_CPU_SYNC); - if (dma_mapping_error(pci->dev, pp->msi_data)) { - dev_err(pci->dev, "Failed to map MSI data\n"); - pp->msi_data = 0; - goto err_free_msi; - } } } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index e1c48b71e0d2..f72447f15dc5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -374,6 +374,8 @@ void dw_pcie_host_deinit(struct pcie_port *pp); int dw_pcie_allocate_domains(struct pcie_port *pp); void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where); +int dw_pcie_allocate_msi(struct pcie_port *pp); +void dw_pcie_free_msi(struct pcie_port *pp); #else static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) { @@ -403,6 +405,15 @@ static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, { return NULL; } + +static int dw_pcie_allocate_msi(struct pcie_port *pp) +{ + return -EINVAL; +} + +static void dw_pcie_free_msi(struct pcie_port *pp) +{ +} #endif #ifdef CONFIG_PCIE_DW_EP