From patchwork Thu Mar 31 16:02:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 555313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82709C433FE for ; Thu, 31 Mar 2022 16:03:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239534AbiCaQFN (ORCPT ); Thu, 31 Mar 2022 12:05:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239592AbiCaQFA (ORCPT ); Thu, 31 Mar 2022 12:05:00 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED1C31F2DEE for ; Thu, 31 Mar 2022 09:03:02 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id h4so20920526edr.3 for ; Thu, 31 Mar 2022 09:03:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=LsohyqOTYtjeLY/FdtDq9Hs2S+lnj2GyDL8XIkBv7/s=; b=SP0DnT+zXeheKpY08siB7JfjgUoxE/xUvqlEpO3D2qYuG3hYVRt8OIEVKqUcSLB4wU bgqFSkgeK3wzbMo4z10UQhP0u/V/Pk9mW2HCjtXkmOZPsMgubNbmyvQofMo+GCMdfllz O4hg0wPw9KOPbo3I34u6BtAh5H09tlr5V671oXSeo54Qwn+/1rjLC2cY62hIyxE7MxCq 8EkK94jwiy8YA6eMRm9IP+VRhCms5NHWwG0jzrOxpncTS+yuVdP7/F2x0ldWipPmQdS7 MLzG+v/XeR5cxmLD0GrnBIHSuRZsMf0YX5YVxKzq1r8AWg94mZIVmJSUsgE2V/md1qiK ZJFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=LsohyqOTYtjeLY/FdtDq9Hs2S+lnj2GyDL8XIkBv7/s=; b=HHwpuptptYy6UTSxHF82jNiqriRBGXZ3KVq4ImbgsVAUKGeZnlvnNrcE9F5p1/+cUz Pm6muXdio6xXukP3u+DukdwhwiP+PcICYMRwwvsWTd2CTB07OVS/ytOwgHXdjBl6XDcR LsHCb9J1YESeTTYgJSK8KiBP0UkoKnZRYeDPZyvF9m6qw8GPwPdBy2rWOGDwvJgeZ1EA REcabsPr+WQFu6LbTCJSHkKqYQSh+fjWIIco2M5qqJjKV8M9t1Ek6svsEYdHwYYQLLug 1bHFJOO1NMFI7+g3lRsGsc5o7chQcYk62w8DAm9pKvzUS3K7ujdmsle2jEr6lvZj38BU PqdA== X-Gm-Message-State: AOAM530qVIBZhtZcHzPT2Cg+wVWBpVlzCPdoRrQC9pxRfntDyPQ0+vM2 Tv+zjlCPZQixiWgqA0aGMEy0Iw== X-Google-Smtp-Source: ABdhPJxB0u62yvNMPi8+ehPNmcqqLZYj23E/zLB13I42inTDaqG5vRRNOI45+sI6ALrh2HwMKlXYEA== X-Received: by 2002:a05:6402:289d:b0:419:437:ef4f with SMTP id eg29-20020a056402289d00b004190437ef4fmr17270028edb.110.1648742579833; Thu, 31 Mar 2022 09:02:59 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id n6-20020aa7c786000000b00410d2403ccfsm11441148eds.21.2022.03.31.09.02.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 09:02:59 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: Kuldeep Singh , Krzysztof Kozlowski Subject: [PATCH v2 1/2] spi: dt-bindings: qcom,spi-geni-qcom: convert to dtschema Date: Thu, 31 Mar 2022 18:02:47 +0200 Message-Id: <20220331160248.716234-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) bindings to DT Schema. The original bindings in TXT were not complete, so add during conversion properties already used in DTS and/or in the driver: reg-names, dmas, interconnects, operating points and power-domains. Signed-off-by: Krzysztof Kozlowski --- Changes since v1: 1. Correct $ref path and remove interconnect minItems (Kuldeep). 2. Remove child tpm device from example. 3. Pad reg hex addresses with 00. --- .../bindings/spi/qcom,spi-geni-qcom.txt | 39 ------ .../bindings/spi/qcom,spi-geni-qcom.yaml | 120 ++++++++++++++++++ 2 files changed, 120 insertions(+), 39 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt deleted file mode 100644 index c8c1e913f4e7..000000000000 --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt +++ /dev/null @@ -1,39 +0,0 @@ -GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) - -The QUP v3 core is a GENI based AHB slave that provides a common data path -(an output FIFO and an input FIFO) for serial peripheral interface (SPI) -mini-core. - -SPI in master mode supports up to 50MHz, up to four chip selects, programmable -data path from 4 bits to 32 bits and numerous protocol variants. - -Required properties: -- compatible: Must contain "qcom,geni-spi". -- reg: Must contain SPI register location and length. -- interrupts: Must contain SPI controller interrupts. -- clock-names: Must contain "se". -- clocks: Serial engine core clock needed by the device. -- #address-cells: Must be <1> to define a chip select address on - the SPI bus. -- #size-cells: Must be <0>. - -SPI Controller nodes must be child of GENI based Qualcomm Universal -Peripharal. Please refer GENI based QUP wrapper controller node bindings -described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml. - -SPI slave nodes must be children of the SPI master node and conform to SPI bus -binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt. - -Example: - spi0: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0xa84000 0x4000>; - interrupts = ; - clock-names = "se"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_spi_2_active>; - pinctrl-1 = <&qup_1_spi_2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml new file mode 100644 index 000000000000..62c4a9598e16 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) + +maintainers: + - Andy Gross + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The QUP v3 core is a GENI based AHB slave that provides a common data path + (an output FIFO and an input FIFO) for serial peripheral interface (SPI) + mini-core. + + SPI in master mode supports up to 50MHz, up to four chip selects, + programmable data path from 4 bits to 32 bits and numerous protocol variants. + + SPI Controller nodes must be child of GENI based Qualcomm Universal + Peripharal. Please refer GENI based QUP wrapper controller node bindings + described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + const: qcom,geni-spi + + clocks: + maxItems: 1 + + clock-names: + const: se + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: qup-core + - const: qup-config + + interrupts: + maxItems: 1 + + operating-points-v2: true + + power-domains: + maxItems: 1 + + reg: + maxItems: 1 + + reg-names: + const: se + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x00880000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + }; + + - | + #include + + spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x00884000 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + };