From patchwork Tue Mar 1 06:14:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 547308 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96DD4C4332F for ; Tue, 1 Mar 2022 06:15:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232545AbiCAGPs (ORCPT ); Tue, 1 Mar 2022 01:15:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232523AbiCAGPr (ORCPT ); Tue, 1 Mar 2022 01:15:47 -0500 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58BC866200 for ; Mon, 28 Feb 2022 22:15:05 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id b9so25171122lfv.7 for ; Mon, 28 Feb 2022 22:15:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MH3Auy6l6ooDxHpVuscOUoj7tDznyoefOt3/IUqiCfw=; b=Sy6nvSHitCY8BQjT1RP5y9q77Vk3SVwJmsamLz5bI0G82oWwGjUu7tNU3sFBYNYG4E 6NuxxG36g/LxubAGKVKGAo7wWAQdq7oAQ6ToPB2ZVJmW8Fm4bW6//CvYePk9dZmBmSKN 6CeNGqnfzMSgKOqBm75SVZn+iVnmQLQO/vUBtrWznmGr6Rz5uJWM0rSxJxItfuoIFkc7 as4BHUOF0yRjrdzzDqqApqhgAw0YL68e5MfgoULHWRQM5A+WSIknza+ZqzJhMSics1EJ kEZL6j+Yl/RaDryijDRi27YbrsZosDDH+65QdafH9iLlyfAS49G1m4fdyJH/rwgejoBC okwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MH3Auy6l6ooDxHpVuscOUoj7tDznyoefOt3/IUqiCfw=; b=kYqCe9rcYvof0BP1EINK5n9hmqhiAnqmYlpEbH6j3+E3XkafdpzVAFV+TRqac0YlX7 aoIA30GrvPykMMmBT0CUDO7zpvFYWkmUCQyDQ7Owsev//xOlgpHl1pfl8c7q5Ai8LpzQ +4cPNLvbdvPVRaqQyL5l0byG1blT/C0LqRPbpG7m/h612FEXE6Qr/IaS5VLlhyTh3cXH 702L4PssbS6deRW7INnzLcByT5G/ijo5QxJQAjjvLQ0h1GCQQAvRjEMYDB/kWOHb783c fX2bfSBRBo/DZRp5Y3QJJACkw3/NxJB9VgvmngbqFvHpdM59EXM3u/o48ZrVa6SBhvLC uZGA== X-Gm-Message-State: AOAM532dthT1+9EhO+OEKVB0TV9ZpYFO7ZfVsbI53mMprEz8de9ArqDn tkgAWQAPVqmyv6rnrwGdOHIOn1z6D2ypPQ== X-Google-Smtp-Source: ABdhPJwqOhufcZwdCSl9kToLrDgNRIY0aY/iSJAoDVkiRzbmsDa+O4EUQH3ih6RFCNjFfP9o3ErAfQ== X-Received: by 2002:ac2:568b:0:b0:443:8232:efff with SMTP id 11-20020ac2568b000000b004438232efffmr14666829lfr.546.1646115303699; Mon, 28 Feb 2022 22:15:03 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id f15-20020ac25ccf000000b004442220c67fsm1318898lfq.27.2022.02.28.22.15.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 22:15:03 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 2/7] arm64: dts: qcom: sm8450: add PCIe0 RC device Date: Tue, 1 Mar 2022 09:14:55 +0300 Message-Id: <20220301061500.2110569-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220301061500.2110569-1-dmitry.baryshkov@linaro.org> References: <20220301061500.2110569-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree node for the first PCIe host found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov Acked-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 98 ++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 38ff1bb532cd..47db7759e543 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -754,6 +754,81 @@ i2c14: i2c@a98000 { }; }; + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sm8450-pcie0"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie0_lane>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + iommus = <&apps_smmu 0x1c00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + power-domain-names = "gdsc"; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "disabled"; + }; + pcie0_phy: phy@1c06000 { compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; reg = <0 0x01c06000 0 0x200>; @@ -1089,6 +1164,29 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + pcie0_default_state: pcie0-default-state { + perst { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio95"; + function = "pcie0_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup_i2c13_data_clk: qup-i2c13-data-clk { pins = "gpio48", "gpio49"; function = "qup13";