From patchwork Wed Feb 23 10:14:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 545351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E445CC4332F for ; Wed, 23 Feb 2022 10:14:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239508AbiBWKPO (ORCPT ); Wed, 23 Feb 2022 05:15:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239510AbiBWKPN (ORCPT ); Wed, 23 Feb 2022 05:15:13 -0500 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38B5A8B6E1 for ; Wed, 23 Feb 2022 02:14:46 -0800 (PST) Received: by mail-lj1-x232.google.com with SMTP id bn33so23811522ljb.6 for ; Wed, 23 Feb 2022 02:14:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bKXCxz8PO7s7Qk0bP2QxK8inFr7HkdpbFAomn9XlFeA=; b=SYmRoB+AQ9vkH7X2hlq89XsfoKRTQiaSb7C6IsJI6VYl7pRXKKkMv/oWn2bxru2XIm Tmo9/csYFFQvykTeLq3CzFwRsHpEl/y4e2QTvoagFVAMhSRKoQP8F8W0Mj+wCbiwEm6j BqcIa0Kl7ltWmOASpDJtDjuQTf7ExZS55AiheYC3y9VbtHEKcUEwwbTK5GQA6nHpvEG2 nhd3PwkecHEbcQSzAJMRTf+yfBnjsCLBGWx5YmiRMeMLxntpQW1gpQLyInIdC9tB3m/f MdxyMYdVo9d74lASdXJtQwS6fy+nGDiRmdzxVwXIXXqwIyDIkHW8cTtb0Wched/Ifs7l awtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bKXCxz8PO7s7Qk0bP2QxK8inFr7HkdpbFAomn9XlFeA=; b=4EaalrWPuVUzHLq2XM1WyXs5g78B2Jgu3bmRyDs1ORKunFQf7YKxo6Rmn8xflJomRo FUts6oh2jdus3lpYfGCzflj5GIuQVdcA2G1WsCsuQbUYS+bRbj/9DNB9ue9IiRiz5I/Q rNn38lbg/OFzTb0lcWvDroxEB+xOfnE8/cISMx828nOp3AxrtLvkH1bQGLrWsuN98kgU lHfnWLrObwZjiKIsk+xXw/9PdXz+1CswvI47aot6c5VOH56vkc9+VMsj/kUF3AcKyDzv Yn/nBEGe7A0tAPO745iLB3nZcC04/FcdPJAS+yxsDpV/t7FXJ5LpDrrCefB3sL2wpirI tFOQ== X-Gm-Message-State: AOAM5331Xx1Ps0FmuPk300ARwhbVR2g+ewjpy3eg4oueXMROb1grex5p 87J5psyPhYFmnRGU2bVZ2D00Ew== X-Google-Smtp-Source: ABdhPJwGkiuibP/yRjiyS+0In7zGWu8vKGOk5v5Yvo9mAgWIYvnW2zN8WqLo+mR88pJiYeolSYmnHw== X-Received: by 2002:a05:651c:14f:b0:23d:8a2a:456d with SMTP id c15-20020a05651c014f00b0023d8a2a456dmr21255258ljd.196.1645611284505; Wed, 23 Feb 2022 02:14:44 -0800 (PST) Received: from eriador.lumag.spb.ru ([94.25.228.217]) by smtp.gmail.com with ESMTPSA id s9sm2060256ljd.79.2022.02.23.02.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 02:14:44 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v6 4/4] PCI: qcom: Add SM8450 PCIe support Date: Wed, 23 Feb 2022 13:14:35 +0300 Message-Id: <20220223101435.447839-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220223101435.447839-1-dmitry.baryshkov@linaro.org> References: <20220223101435.447839-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On SM8450 platform PCIe hosts do not use all the clocks (and add several additional clocks), so expand the driver to handle these requirements. PCIe0 and PCIe1 hosts use different sets of clocks, so separate entries are required. Reviewed-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 57 ++++++++++++++++++++------ 1 file changed, 44 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 7e97820eb575..0bb6d0e14cbb 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -161,7 +161,7 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[7]; + struct clk_bulk_data clks[9]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -195,7 +195,10 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; unsigned int pipe_clk_need_muxing:1; + unsigned int has_tbu_clk:1; unsigned int has_ddrss_sf_tbu_clk:1; + unsigned int has_aggre0_clk:1; + unsigned int has_aggre1_clk:1; }; struct qcom_pcie { @@ -1146,6 +1149,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + unsigned int idx; int ret; res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); @@ -1159,18 +1163,22 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret) return ret; - res->clks[0].id = "aux"; - res->clks[1].id = "cfg"; - res->clks[2].id = "bus_master"; - res->clks[3].id = "bus_slave"; - res->clks[4].id = "slave_q2a"; - res->clks[5].id = "tbu"; - if (pcie->cfg->has_ddrss_sf_tbu_clk) { - res->clks[6].id = "ddrss_sf_tbu"; - res->num_clks = 7; - } else { - res->num_clks = 6; - } + idx = 0; + res->clks[idx++].id = "aux"; + res->clks[idx++].id = "cfg"; + res->clks[idx++].id = "bus_master"; + res->clks[idx++].id = "bus_slave"; + res->clks[idx++].id = "slave_q2a"; + if (pcie->cfg->has_tbu_clk) + res->clks[idx++].id = "tbu"; + if (pcie->cfg->has_ddrss_sf_tbu_clk) + res->clks[idx++].id = "ddrss_sf_tbu"; + if (pcie->cfg->has_aggre0_clk) + res->clks[idx++].id = "aggre0"; + if (pcie->cfg->has_aggre1_clk) + res->clks[idx++].id = "aggre1"; + + res->num_clks = idx; ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); if (ret < 0) @@ -1236,6 +1244,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) goto err_disable_clocks; } + /* Wait for reset to complete, required on SM8450 */ + usleep_range(1000, 1500); + /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); @@ -1509,15 +1520,33 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { static const struct qcom_pcie_cfg sdm845_cfg = { .ops = &ops_2_7_0, + .has_tbu_clk = true, }; static const struct qcom_pcie_cfg sm8250_cfg = { + .ops = &ops_1_9_0, + .has_tbu_clk = true, + .has_ddrss_sf_tbu_clk = true, +}; + +static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, + .pipe_clk_need_muxing = true, + .has_aggre0_clk = true, + .has_aggre1_clk = true, +}; + +static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { + .ops = &ops_1_9_0, + .has_ddrss_sf_tbu_clk = true, + .pipe_clk_need_muxing = true, + .has_aggre1_clk = true, }; static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, + .has_tbu_clk = true, .pipe_clk_need_muxing = true, }; @@ -1628,6 +1657,8 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg }, + { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg }, + { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg }, { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, { } };