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[188.155.181.108]) by smtp.gmail.com with ESMTPSA id j8sm6680745edw.40.2022.02.19.10.42.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Feb 2022 10:42:28 -0800 (PST) From: Krzysztof Kozlowski To: Alim Akhtar , Avri Altman , Rob Herring , Krzysztof Kozlowski , Wei Xu , Andy Gross , Bjorn Andersson , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , "James E.J. Bottomley" , "Martin K. Petersen" , Chanho Park , Srinivas Kandagatla , Jan Kotas , linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [RFC PATCH 1/8] dt-bindings: ufs: add common platform bindings Date: Sat, 19 Feb 2022 19:42:17 +0100 Message-Id: <20220219184224.44339-2-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220219184224.44339-1-krzysztof.kozlowski@canonical.com> References: <20220219184224.44339-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add bindings for common parts (platform) of Universal Flash Storage (UFS) Host Controllers in dtschema format. The 'freq-table-hz' is not correct in dtschema, because '-hz' suffix defines uint32 type, not an array. Therefore deprecate 'freq-table-hz' and use 'freq-table' instead. Include also the bindings directory in UFS maintainers entry. Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/ufs/ti,j721e-ufs.yaml | 2 +- .../devicetree/bindings/ufs/ufs-common.yaml | 86 +++++++++++++++++++ .../devicetree/bindings/ufs/ufs-hisi.txt | 4 +- MAINTAINERS | 1 + 4 files changed, 90 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-common.yaml diff --git a/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml b/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml index 4d13e6bc1c50..dc93fe2d3458 100644 --- a/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml @@ -80,7 +80,7 @@ examples: compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; reg = <0x0 0x4000 0x0 0x10000>; interrupts = ; - freq-table-hz = <19200000 19200000>; + freq-table = <19200000 19200000>; power-domains = <&k3_pds 277>; clocks = <&k3_clks 277 1>; assigned-clocks = <&k3_clks 277 1>; diff --git a/Documentation/devicetree/bindings/ufs/ufs-common.yaml b/Documentation/devicetree/bindings/ufs/ufs-common.yaml new file mode 100644 index 000000000000..66d0612b9991 --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/ufs-common.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/ufs-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common properties for Universal Flash Storage (UFS) Host Controllers + +maintainers: + - Alim Akhtar + - Avri Altman + +properties: + clocks: true + + clock-names: true + + freq-table-hz: + deprecated: true + description: + Use freq-table. + + freq-table: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 64 + description: | + Array of operating frequencies in Hz stored in the same order + as the clocks property. If this property is not defined or a value in the + array is "0" then it is assumed that the frequency is set by the parent + clock or a fixed rate clock source. + + interrupts: + maxItems: 1 + + lanes-per-direction: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + default: 2 + description: + Number of lanes available per direction. Note that it is assume same + number of lanes is used both directions at once. + + vdd-hba-supply: + description: + Phandle to UFS host controller supply regulator node. + + vcc-supply: + description: + Phandle to VCC supply regulator node. + + vccq-supply: + description: + Phandle to VCCQ supply regulator node. + + vccq2-supply: + description: + Phandle to VCCQ2 supply regulator node. + + vcc-supply-1p8: + type: boolean + description: + For embedded UFS devices, valid VCC range is 1.7-1.95V or 2.7-3.6V. This + boolean property when set, specifies to use low voltage range of + 1.7-1.95V. Note for external UFS cards this property is invalid and valid + VCC range is always 2.7-3.6V. + + vcc-max-microamp: + description: + Specifies max. load that can be drawn from VCC supply. + + vccq-max-microamp: + description: + Specifies max. load that can be drawn from VCCQ supply. + + vccq2-max-microamp: + description: + Specifies max. load that can be drawn from VCCQ2 supply. + +dependencies: + freq-table: [ 'clocks' ] + +required: + - interrupts + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt index 0b83df1a5418..7e9cf4cff3d3 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt +++ b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt @@ -14,7 +14,7 @@ Required properties: - clocks : List of phandle and clock specifier pairs - clock-names : List of clock input name strings sorted in the same order as the clocks property. "ref_clk", "phy_clk" is optional -- freq-table-hz : Array of operating frequencies stored in the same +- freq-table : Array of operating frequencies stored in the same order as the clocks property. If this property is not defined or a value in the array is "0" then it is assumed that the frequency is set by the parent clock or a @@ -35,7 +35,7 @@ Example: clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0>, <0 0>; + freq-table = <0 0 0 0>; /* offset: 0x84; bit: 12 */ resets = <&crg_rst 0x84 12>; reset-names = "rst"; diff --git a/MAINTAINERS b/MAINTAINERS index cae5b0c8400d..542174f434ce 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20015,6 +20015,7 @@ R: Alim Akhtar R: Avri Altman L: linux-scsi@vger.kernel.org S: Supported +F: Documentation/devicetree/bindings/ufs/ F: Documentation/scsi/ufs.rst F: drivers/scsi/ufs/