From patchwork Fri Aug 20 20:49:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 500454 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26F8EC4320E for ; Fri, 20 Aug 2021 20:49:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 07A756115B for ; Fri, 20 Aug 2021 20:49:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241041AbhHTUu0 (ORCPT ); Fri, 20 Aug 2021 16:50:26 -0400 Received: from relay01.th.seeweb.it ([5.144.164.162]:36961 "EHLO relay01.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240868AbhHTUuV (ORCPT ); Fri, 20 Aug 2021 16:50:21 -0400 Received: from localhost.localdomain (83.6.167.97.neoplus.adsl.tpnet.pl [83.6.167.97]) by m-r1.th.seeweb.it (Postfix) with ESMTPA id 0EBC51F548; Fri, 20 Aug 2021 22:49:41 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/17] arm64: dts: qcom: sm6350: Add cpufreq-hw support Date: Fri, 20 Aug 2021 22:49:17 +0200 Message-Id: <20210820204926.235192-9-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210820204926.235192-1-konrad.dybcio@somainline.org> References: <20210820204926.235192-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add cpufreq-hw node and assign qcom,freq-domain properties to CPUs to enable CPU clock scaling. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index e70b1f09a488..f7965d5fb341 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -41,6 +41,7 @@ CPU0: cpu@0 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; @@ -59,6 +60,7 @@ CPU1: cpu@100 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; @@ -74,6 +76,7 @@ CPU2: cpu@200 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; @@ -89,6 +92,7 @@ CPU3: cpu@300 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; @@ -104,6 +108,7 @@ CPU4: cpu@400 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; @@ -119,6 +124,7 @@ CPU5: cpu@500 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; @@ -135,6 +141,7 @@ CPU6: cpu@600 { capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <703>; next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; @@ -150,6 +157,7 @@ CPU7: cpu@700 { capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <703>; next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; @@ -622,6 +630,16 @@ rpmhcc: clock-controller { clocks = <&xo_board>; }; }; + + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,cpufreq-hw"; + reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; timer {