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[73.25.156.94]) by smtp.gmail.com with ESMTPSA id j3sm4259943pfc.10.2021.07.29.11.35.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jul 2021 11:35:25 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , Caleb Connolly , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jordan Crouse , Jonathan Marek , Sai Prakash Ranjan , Bjorn Andersson , Sharat Masetty , Akhil P Oommen , linux-kernel@vger.kernel.org (open list) Subject: [PATCH] drm/msm: Disable frequency clamping on a630 Date: Thu, 29 Jul 2021 11:39:40 -0700 Message-Id: <20210729183942.2839925-1-robdclark@gmail.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark The more frequent frequency transitions resulting from clamping freq to minimum when the GPU is idle seems to be causing some issue with the bus getting voted off when it should be on. (An enable racing with an async disable?) This might be a problem outside of the GPU, as I can't reproduce this on a618 which uses the same GMU fw and same mechanism to communicate with GMU to set opp. For now, just revert to previous devfreq behavior on a630 until the issue is understood. Reported-by: Caleb Connolly Fixes: 9bc95570175a ("drm/msm: Devfreq tuning") Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ drivers/gpu/drm/msm/msm_gpu.h | 2 ++ drivers/gpu/drm/msm/msm_gpu_devfreq.c | 12 ++++++++++++ 3 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 748665232d29..9fd08b413010 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -945,6 +945,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, pm_runtime_use_autosuspend(dev); pm_runtime_enable(dev); + if (adreno_is_a630(adreno_gpu)) + gpu->devfreq.disable_freq_clamping = true; + return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, adreno_gpu->info->name, &adreno_gpu_config); } diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 0e4b45bff2e6..7e11b667f939 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -112,6 +112,8 @@ struct msm_gpu_devfreq { * it is inactive. */ unsigned long idle_freq; + + bool disable_freq_clamping; }; struct msm_gpu { diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c index 0a1ee20296a2..a832af436251 100644 --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c @@ -94,6 +94,12 @@ void msm_devfreq_init(struct msm_gpu *gpu) if (!gpu->funcs->gpu_busy) return; + /* Revert to previous polling interval if we aren't using freq clamping + * to preserve previous behavior + */ + if (gpu->devfreq.disable_freq_clamping) + msm_devfreq_profile.polling_ms = 10; + msm_devfreq_profile.initial_freq = gpu->fast_rate; /* @@ -151,6 +157,9 @@ void msm_devfreq_active(struct msm_gpu *gpu) unsigned int idle_time; unsigned long target_freq = df->idle_freq; + if (gpu->devfreq.disable_freq_clamping) + return; + /* * Hold devfreq lock to synchronize with get_dev_status()/ * target() callbacks @@ -186,6 +195,9 @@ void msm_devfreq_idle(struct msm_gpu *gpu) struct msm_gpu_devfreq *df = &gpu->devfreq; unsigned long idle_freq, target_freq = 0; + if (gpu->devfreq.disable_freq_clamping) + return; + /* * Hold devfreq lock to synchronize with get_dev_status()/ * target() callbacks