From patchwork Thu Jul 22 02:42:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 483854 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6762877jao; Wed, 21 Jul 2021 19:44:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzpNBAwvzTr32FeXHVBnO+/R+QnQAH7TPOgU1WDEFX660+KOnBzT2vgulhbwshai6PN/Rts X-Received: by 2002:a5d:9648:: with SMTP id d8mr28369759ios.171.1626921863078; Wed, 21 Jul 2021 19:44:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626921863; cv=none; d=google.com; s=arc-20160816; b=h3u9ut++RerSgi1vLG8mMHeLhOv/4a+krv4A4glsP/y1pt+PVuxmeZTd/wEEkA8SWN GBlPJPvcld0+O9GNWvKNkhH0Y1vKrxoisjInhPct8CCXgHkbN8ju3fqaPzGg5Xs5U1aj Um8I848cfyB5okrzNV2x8s6/EyjlPdwY9rUQT026aah36Ke+nRkaKEH3LZMe5EGNVDkZ fVx49lele1fKkzh01gakn7XH2uSrJ7/1wf8re6Aw5ys4VJo7V9EiqKgK/L54IZ1Xf/Yq OW6Z8nR5JQHGHC6zjy6ewhQCNeN2S98QwIZe1L9XVT/xaOPNDxjyvO42AZLu7204ot8N Pk7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bo1WH90B2Q6BpI8Vp15t4ugWjGrNTTsDZhz3C9CMTkc=; b=uuo6XQJaykVMuOEIQe7HYI2z1Nemw3r/PaJb1Te4sc6tvvdYOmjz4oNvojAGLanwKZ digCdB37ClMX6j4P2alwRbExvNYV+oteF+jLtoyqCjoMrL0iBerev+VRZVujP8xoWqRh EnO7Fqyq/5vYQQ8ii28IrxVM1im0ElFx1NhDRxGcve0JBekltu71EOQW6W8geUH01/Qm pOQ7WDa0scXUGX/Gt4BxBNzaKHhYxUOEzK8k45JZbg7vhCu3fOoxw+XM8sFftYURyqI0 qlYVY8eKWmExIT/7bW69xbu/3zyZ/FCrp85vC9LT0pKkqWFITxssCz76qm1osJ2vIeW9 U6rw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EM1kT5yb; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z7si1358727ilq.32.2021.07.21.19.44.22; Wed, 21 Jul 2021 19:44:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EM1kT5yb; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231128AbhGVCDp (ORCPT + 17 others); Wed, 21 Jul 2021 22:03:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230506AbhGVCDo (ORCPT ); Wed, 21 Jul 2021 22:03:44 -0400 Received: from mail-ot1-x330.google.com (mail-ot1-x330.google.com [IPv6:2607:f8b0:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC466C061799 for ; Wed, 21 Jul 2021 19:44:15 -0700 (PDT) Received: by mail-ot1-x330.google.com with SMTP id b18-20020a0568303112b02904cf73f54f4bso1020818ots.2 for ; Wed, 21 Jul 2021 19:44:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bo1WH90B2Q6BpI8Vp15t4ugWjGrNTTsDZhz3C9CMTkc=; b=EM1kT5ybuQduKHIs+KTxthW8o24JaLpX36RVLazTaIPkm1XaeZ/O8x8O22//Jlmydt fdgef1G69braOKl4B6enqe4hvkNuy1tnBVJd13g1DQNz3TDC+lQEy5LHxbfMmgbiNoYn 8DuBs8vtFhiSN1JAC+/tCPEKCIaiMo/mYOrI9elkGbIg1vy6wBKS1JvugJD1nUemzo3o 6GzkiLRvrEKRdjB4QEv2nZDvEfXyeRy5TobfcejNfduQJrcvCRcnUKKroFCnpB61w9gZ //x4Y6sv+oZMMFhN4VAyk9WRvayUo57NvV8tnfHpxYfhz3t1s/LYUeSpuGyxXwPC5eWX hRYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bo1WH90B2Q6BpI8Vp15t4ugWjGrNTTsDZhz3C9CMTkc=; b=mp+MlIHrj7rw0ZosCiWe7MJ5ZfuUhzZO5MsuRuNxnp+wEYmBPR/KcB2G908hjloqzy txnR/6ny2910XlJAkxGCLR3+BnYuLmo+wiOd7iys83Tq/1KAHiNOCgjDdYnWdoRjw6BU J3i0yGUbKMeTfgrTtuFh5Cse+w6AKkGf2AHw3YILDIvMOFKJdX29f3hjrIoOjQjfbqns sMzrl7m8Vy2sC0VswahXEVcuE8VQQ1lJyQeohk3b/aivWvPQR3VxT/5udWMiLAWxOCnX 1S+3sZd1dZ1jt0b93zksX54oJep9BcUP0kl4VUSJYtTbj8bCxTLHYeww26b+ynCY3CJr LLXw== X-Gm-Message-State: AOAM531UX0GFqnE+BD32jQdPrl2oD3MZRkMwwjpkjQRhpZ+vgBo1dI8K ara01PxQPN3F0BRFt6G/nEYIog== X-Received: by 2002:a9d:63c6:: with SMTP id e6mr27408331otl.295.1626921855164; Wed, 21 Jul 2021 19:44:15 -0700 (PDT) Received: from localhost.localdomain (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id u18sm5346519oif.9.2021.07.21.19.44.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 19:44:14 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Stephen Boyd , Abhinav Kumar Cc: Kuogee Hsieh , Tanmay Shah , Chandan Uddaraju , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] drm/msm/dp: Store each subblock in the io region Date: Wed, 21 Jul 2021 19:42:26 -0700 Message-Id: <20210722024227.3313096-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210722024227.3313096-1-bjorn.andersson@linaro.org> References: <20210722024227.3313096-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Not all platforms has DP_P0 at offset 0x1000 from the beginning of the DP block. So dss_io_data into representing each of the sub-regions, to make it possible in the next patch to specify each of the sub-regions individually. Signed-off-by: Bjorn Andersson --- drivers/gpu/drm/msm/dp/dp_catalog.c | 64 +++++++++-------------------- drivers/gpu/drm/msm/dp/dp_parser.c | 30 ++++++++++++-- drivers/gpu/drm/msm/dp/dp_parser.h | 10 ++++- 3 files changed, 54 insertions(+), 50 deletions(-) -- 2.29.2 diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index ca96e3514790..23458b0ddc37 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -24,15 +24,6 @@ #define DP_INTERRUPT_STATUS_ACK_SHIFT 1 #define DP_INTERRUPT_STATUS_MASK_SHIFT 2 -#define MSM_DP_CONTROLLER_AHB_OFFSET 0x0000 -#define MSM_DP_CONTROLLER_AHB_SIZE 0x0200 -#define MSM_DP_CONTROLLER_AUX_OFFSET 0x0200 -#define MSM_DP_CONTROLLER_AUX_SIZE 0x0200 -#define MSM_DP_CONTROLLER_LINK_OFFSET 0x0400 -#define MSM_DP_CONTROLLER_LINK_SIZE 0x0C00 -#define MSM_DP_CONTROLLER_P0_OFFSET 0x1000 -#define MSM_DP_CONTROLLER_P0_SIZE 0x0400 - #define DP_INTERRUPT_STATUS1 \ (DP_INTR_AUX_I2C_DONE| \ DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \ @@ -66,82 +57,77 @@ void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *d { struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + struct dss_io_data *dss = &catalog->io->dp_controller; - msm_disp_snapshot_add_block(disp_state, catalog->io->dp_controller.len, - catalog->io->dp_controller.base, "dp_ctrl"); + msm_disp_snapshot_add_block(disp_state, dss->ahb_len, dss->ahb, "dp_ahb"); + msm_disp_snapshot_add_block(disp_state, dss->aux_len, dss->aux, "dp_aux"); + msm_disp_snapshot_add_block(disp_state, dss->link_len, dss->link, "dp_link"); + msm_disp_snapshot_add_block(disp_state, dss->p0_len, dss->p0, "dp_p0"); } static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_AUX_OFFSET; - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.aux + offset); } static inline void dp_write_aux(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_AUX_OFFSET; /* * To make sure aux reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.aux + offset); } static inline u32 dp_read_ahb(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_AHB_OFFSET; - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.ahb + offset); } static inline void dp_write_ahb(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_AHB_OFFSET; /* * To make sure phy reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.ahb + offset); } static inline void dp_write_p0(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_P0_OFFSET; /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.p0 + offset); } static inline u32 dp_read_p0(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_P0_OFFSET; /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.p0 + offset); } static inline u32 dp_read_link(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_LINK_OFFSET; - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.link + offset); } static inline void dp_write_link(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_LINK_OFFSET; /* * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.link + offset); } /* aux related catalog functions */ @@ -276,29 +262,21 @@ static void dump_regs(void __iomem *base, int len) void dp_catalog_dump_regs(struct dp_catalog *dp_catalog) { - u32 offset, len; struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + struct dss_io_data *io = &catalog->io->dp_controller; pr_info("AHB regs\n"); - offset = MSM_DP_CONTROLLER_AHB_OFFSET; - len = MSM_DP_CONTROLLER_AHB_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->ahb, io->ahb_len); pr_info("AUXCLK regs\n"); - offset = MSM_DP_CONTROLLER_AUX_OFFSET; - len = MSM_DP_CONTROLLER_AUX_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->aux, io->aux_len); pr_info("LCLK regs\n"); - offset = MSM_DP_CONTROLLER_LINK_OFFSET; - len = MSM_DP_CONTROLLER_LINK_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->link, io->link_len); pr_info("P0CLK regs\n"); - offset = MSM_DP_CONTROLLER_P0_OFFSET; - len = MSM_DP_CONTROLLER_P0_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->p0, io->p0_len); } u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog) @@ -492,8 +470,7 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, bit = BIT(pattern - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; /* Poll for mainlink ready status */ - ret = readx_poll_timeout(readl, catalog->io->dp_controller.base + - MSM_DP_CONTROLLER_LINK_OFFSET + + ret = readx_poll_timeout(readl, catalog->io->dp_controller.link + REG_DP_MAINLINK_READY, data, data & bit, POLLING_SLEEP_US, POLLING_TIMEOUT_US); @@ -540,8 +517,7 @@ bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog) struct dp_catalog_private, dp_catalog); /* Poll for mainlink ready status */ - ret = readl_poll_timeout(catalog->io->dp_controller.base + - MSM_DP_CONTROLLER_LINK_OFFSET + + ret = readl_poll_timeout(catalog->io->dp_controller.link + REG_DP_MAINLINK_READY, data, data & DP_MAINLINK_READY_FOR_VIDEO, POLLING_SLEEP_US, POLLING_TIMEOUT_US); diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index e68dacef547c..1a10901ae574 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -11,6 +11,15 @@ #include "dp_parser.h" #include "dp_reg.h" +#define DP_DEFAULT_AHB_OFFSET 0x0000 +#define DP_DEFAULT_AHB_SIZE 0x0200 +#define DP_DEFAULT_AUX_OFFSET 0x0200 +#define DP_DEFAULT_AUX_SIZE 0x0200 +#define DP_DEFAULT_LINK_OFFSET 0x0400 +#define DP_DEFAULT_LINK_SIZE 0x0C00 +#define DP_DEFAULT_P0_OFFSET 0x1000 +#define DP_DEFAULT_P0_SIZE 0x0400 + static const struct dp_regulator_cfg sdm845_dp_reg_cfg = { .num = 2, .regs = { @@ -48,12 +57,25 @@ static int dp_parser_ctrl_res(struct dp_parser *parser) struct dp_io *io = &parser->io; struct dss_io_data *dss = &io->dp_controller; - dss->base = dp_ioremap(pdev, 0, &dss->len); - if (IS_ERR(dss->base)) { - DRM_ERROR("unable to remap dp io region: %pe\n", dss->base); - return PTR_ERR(dss->base); + dss->ahb = dp_ioremap(pdev, 0, &dss->ahb_len); + if (IS_ERR(dss->ahb)) { + DRM_ERROR("unable to remap ahb region: %pe\n", dss->ahb); + return PTR_ERR(dss->ahb); } + if (dss->ahb_len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) { + DRM_ERROR("legacy memory region not large enough\n"); + return -EINVAL; + } + + dss->ahb_len = DP_DEFAULT_AHB_SIZE; + dss->aux = dss->ahb + DP_DEFAULT_AUX_OFFSET; + dss->aux_len = DP_DEFAULT_AUX_SIZE; + dss->link = dss->ahb + DP_DEFAULT_LINK_OFFSET; + dss->link_len = DP_DEFAULT_LINK_SIZE; + dss->p0 = dss->ahb + DP_DEFAULT_P0_OFFSET; + dss->p0_len = DP_DEFAULT_P0_SIZE; + io->phy = devm_phy_get(&pdev->dev, "dp"); if (IS_ERR(io->phy)) return PTR_ERR(io->phy); diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index dc62e70b1640..3266b529c090 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -26,8 +26,14 @@ enum dp_pm_type { }; struct dss_io_data { - size_t len; - void __iomem *base; + void __iomem *ahb; + size_t ahb_len; + void __iomem *aux; + size_t aux_len; + void __iomem *link; + size_t link_len; + void __iomem *p0; + size_t p0_len; }; static inline const char *dp_parser_pm_name(enum dp_pm_type module)