From patchwork Mon Jul 5 01:21:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 470189 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp3547244jao; Sun, 4 Jul 2021 18:25:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzlM6PV+j6aeH2iNzk2o1TL3Wk++K7TpQz5J9c5DriQFjlOyRkzoZhknElV0TvegkLCPeu/ X-Received: by 2002:a05:6402:1688:: with SMTP id a8mr11172805edv.4.1625448325995; Sun, 04 Jul 2021 18:25:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625448325; cv=none; d=google.com; s=arc-20160816; b=DgotbUAPcbfqe5jf9u3Ita6K3TY0gaEPlr3QR8PC7OncMxCAVVgUW4r2uFTuo0Iy++ M19tKrxOfePLghp1+RvBpoAa2GRG69mpQS9SU/V1Et0MmeP/nSfMDsKBiiXn9SNg1hux wbFZs/v4InXQOS7IKeifwP9U033bjqcBgAirgfnbJEIDcG1GFoxaCAJWucHikGgFockm UVVNOh42c73vrrpLYmfc9KZYzO3Wbo3NGA95Z3sdK3jlHj38SUi9rhe73m5kYmYAALdA 7Icim9t7SwIP7IhFoyBWb/RPkp3f2f1/2YQRpMiqxxtBIKtnfhma2mJvH0h8irQU4blN J7Wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hWilg6YaSqF46jkkdfsQMZj3MRMuOXV7b9r5SgXMa54=; b=y95FGMZcnjjQGXIPU2ow8OZJGISncssnnp8RuAdjDP9MuXz7HGk44gwHSd5L0BH1if 7aoq6187bPthMZ8J/wpDcx3J8ZIZBKTZMjSEcuJY9JfNsS0TcSnLxgJnSGlekyDb2q0o 1w07sr4ZzbTAsHJy71JkbV9/PBWw4+0dkNkEsX6PGCq6PqjkIofOpx/MzECKGoxDzjIl nCXl4xIG0sz4/GJGHtm6RXAYqbvlh6nQbwjG2cj69L2bM/S9TyrcG89/rguDkrSQp4dn o1kBjdtSJSbZqizjxe4z91nFyRIXDjbF76CHjsuGGdfn826L4LjwPLt3oJUMCNCUESJi DLNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EnvfI8V2; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id cn17si4805170edb.13.2021.07.04.18.25.25; Sun, 04 Jul 2021 18:25:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EnvfI8V2; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229904AbhGEB2B (ORCPT + 17 others); Sun, 4 Jul 2021 21:28:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229895AbhGEB2A (ORCPT ); Sun, 4 Jul 2021 21:28:00 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09A88C061764 for ; Sun, 4 Jul 2021 18:25:24 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id k8so22351553lja.4 for ; Sun, 04 Jul 2021 18:25:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hWilg6YaSqF46jkkdfsQMZj3MRMuOXV7b9r5SgXMa54=; b=EnvfI8V2bPWc9k1MbhMwIbKqEM3HB+QDvlAJlmBpKXxIUUi7VswbQix+Nt+v2Kx0Wv 00+/1iAdyCaE5hJVX2bIXh6IypT/PeRK/oAq5iwC8Yc+rglDUYkuDtiBEdj/Y7R/xx93 dWR5I6Mcmv0olQSCvBsFL9dHRwsLuQ5fEqjJzDt/qUNwA0JdwJ2LSdW66Jvzw7ULWice R9nEolCErSaXGu20CWG6xMUYcG0omZUVIHCXPylt16xTywVC9YwmE1+RWtjrvYntTQVJ CJf8HVMZdc4ca4dYqRT+od85O4lIqRbZ+QfBmZtVnL1C8+Du0U7Tc24Q6KI8bMd2wiWG QUuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hWilg6YaSqF46jkkdfsQMZj3MRMuOXV7b9r5SgXMa54=; b=CA1PCJ77nEYqg1Dho9DBxYDvscCiJjuPRKQls3hYzCHQEiaLPzbsFLErUh8XPfYJ5k Sp7YRbSro4e/Viy7zjB4y5V++KDWW8O3J478dkj/ouLgvVSov57AFeZ4fNA0zz//K1NZ qIxc/7n2evlevyZxBUXGnMxQdz2vJMQtcvbjU6fbN+ISiBY9Jpq8i97IUhCTS41XFISS A0GWxy+sbh1pTPfwBF3t9VntbFEqRnOwcCzLeukllGU/OWYJnj3qoKRMumAYBVxSIgXj yglvJ8HLCWOB2uK1aAwyMeYOeEKLEM4VXOY9280Kr8UVHxsrqJQiQyaudbkwT4aRW5Tf 7hWQ== X-Gm-Message-State: AOAM531WsfiEEXIWv18bXt2G33L1brofbbiOeftmwgUJ8nuQKkuWJHuB GjrCStnck/C79Hjbulkiwyll3W9lRc7gkw== X-Received: by 2002:a2e:a54d:: with SMTP id e13mr9196749ljn.272.1625448322416; Sun, 04 Jul 2021 18:25:22 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id c7sm1004345lfm.50.2021.07.04.18.25.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Jul 2021 18:25:22 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 20/22] drm/msm/dpu: fix smart dma support Date: Mon, 5 Jul 2021 04:21:13 +0300 Message-Id: <20210705012115.4179824-21-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210705012115.4179824-1-dmitry.baryshkov@linaro.org> References: <20210705012115.4179824-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Downstream driver uses dpu->caps->smart_dma_rev to update sspp->cap->features with the bit corresponding to the supported SmartDMA version. Upstream driver does not do this, resulting in SSPP subdriver not enbaling setup_multirect callback. Make SSPP subdriver check global smart_dma_rev to decide if setup_multirect should be enabled. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 10 +++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 16 ++++++++++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 +++++---- 3 files changed, 22 insertions(+), 13 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index b8e0fece1f0b..d2321648b8d2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -185,7 +185,7 @@ static const struct dpu_caps sdm845_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, + .smart_dma_rev = DPU_SMART_DMA_V2, .ubwc_version = DPU_HW_UBWC_VER_20, .has_src_split = true, .has_dim_layer = true, @@ -203,7 +203,7 @@ static const struct dpu_caps sc7180_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x9, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, + .smart_dma_rev = DPU_SMART_DMA_V2, .ubwc_version = DPU_HW_UBWC_VER_20, .has_dim_layer = true, .has_idle_pc = true, @@ -217,7 +217,7 @@ static const struct dpu_caps sm8150_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ + .smart_dma_rev = DPU_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_30, .has_src_split = true, .has_dim_layer = true, @@ -235,7 +235,7 @@ static const struct dpu_caps sm8250_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ + .smart_dma_rev = DPU_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_40, .has_src_split = true, .has_dim_layer = true, @@ -251,7 +251,7 @@ static const struct dpu_caps sc7280_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, + .smart_dma_rev = DPU_SMART_DMA_V2, .ubwc_version = DPU_HW_UBWC_VER_30, .has_dim_layer = true, .has_idle_pc = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index f3c5aa3f4b3f..66d7b43c0019 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -70,6 +70,18 @@ enum { DPU_HW_UBWC_VER_40 = 0x400, }; +/** + * SmartDMA support + * @DPU_SMART_DMA_UNSUPPORTED, SmartDMA not support + * @DPU_SMART_DMA_V1, SmartDMA 1.0 support + * @DPU_SMART_DMA_V2, SmartDMA 2.0 support + */ +enum { + DPU_SMART_DMA_UNSUPPORTED, + DPU_SMART_DMA_V1, + DPU_SMART_DMA_V2, +}; + /** * MDP TOP BLOCK features * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe @@ -104,8 +116,6 @@ enum { * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect - * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support - * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec * @DPU_SSPP_CDP Supports client driven prefetch @@ -124,8 +134,6 @@ enum { DPU_SSPP_QOS, DPU_SSPP_QOS_8LVL, DPU_SSPP_EXCL_RECT, - DPU_SSPP_SMART_DMA_V1, - DPU_SSPP_SMART_DMA_V2, DPU_SSPP_TS_PREFILL, DPU_SSPP_TS_PREFILL_REC1, DPU_SSPP_CDP, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 2be43d5a235a..f93cdeb08ac7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -648,7 +648,8 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx, } static void _setup_layer_ops(struct dpu_hw_pipe *c, - unsigned long features) + unsigned long features, + int smart_dma_rev) { if (test_bit(DPU_SSPP_SRC, &features)) { c->ops.setup_format = dpu_hw_sspp_setup_format; @@ -669,8 +670,8 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c, test_bit(DPU_SSPP_CSC_10BIT, &features)) c->ops.setup_csc = dpu_hw_sspp_setup_csc; - if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) || - test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features)) + if (smart_dma_rev == DPU_SMART_DMA_V1 || + smart_dma_rev == DPU_SMART_DMA_V2) c->ops.setup_multirect = dpu_hw_sspp_setup_multirect; if (test_bit(DPU_SSPP_SCALER_QSEED3, &features) || @@ -731,7 +732,7 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, hw_pipe->mdp = &catalog->mdp[0]; hw_pipe->idx = idx; hw_pipe->cap = cfg; - _setup_layer_ops(hw_pipe, hw_pipe->cap->features); + _setup_layer_ops(hw_pipe, hw_pipe->cap->features, catalog->caps->smart_dma_rev); return hw_pipe; }