From patchwork Thu Jun 24 14:57:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466349 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536738jao; Thu, 24 Jun 2021 07:57:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwSPVdCo7joyLfASmzntLzdWcL0iwg+GwspAqURfbeaYoY4kZo51HSr9vVNW2t2juDlRe2/ X-Received: by 2002:a92:c14e:: with SMTP id b14mr2592311ilh.49.1624546662895; Thu, 24 Jun 2021 07:57:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624546662; cv=none; d=google.com; s=arc-20160816; b=zMhjj8PlyM8O/Cq1InGxKwbU5sRdebKkX1/Hcb2KD7tY0rErXFc/wpRLj9A2L5Hljr vIzUehV+8l0qZmLu0RFApV3EGo21EomHk6HWLNdcMrachNsgPM3bgjy4cAn0paBleYNt TLRJlNyUBixK4VB3rJ54g/sKJKlNEFRG72CRoXu3T/dWvNgCPeRsOEn4ZwWRxvMYx+21 ooKahb+sKvYQmt11u29c5ZjM4u5ChfESx/uWON85PvWLSloKW7eZ8Ug44wysTsz8mMvv Dx7HnCS/500o4oOI7Qf2/wSzuQ7C3HfoQg1Lq88ov6wghU/Vdh8/nZN8PCksDsBxQ/rM mNeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=zdxuO3FXcMYXnxkLpZHy8crKZag9SkX+E8b620Ln9pw=; b=NkioWh4qRGah8bBgtYGs85sRVhwB61sKaAgoFwtrhAAYlYjFFVzAf24ouJR68EEu+A z1xMUm5fYrSExcnsBdBNxDxK+IjlvtcTukjXpokl1nZAFiivGjb0ZbMKOufclCPVXYoS hnivf/fiIQGudZfpUY3CkEmUvsMu9ya2vteMGI0TAxBMs5sbatQGlBdvnBRrMDQbMz98 V/S0eKJB+sVq/i89uz+rnVXAawxpVl5RdoQNU1nyvnkmW7VLHfHiQACuozO7WzudegsJ mYtS41TkzpIfJEOLLXir3uSvA05xSQpljkYnyNzKN4Ij/rb9WaEcEbG3L/wwP1kZXWw1 LopA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cykGp7ub; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id j25si3607720jaj.93.2021.06.24.07.57.42; Thu, 24 Jun 2021 07:57:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cykGp7ub; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230170AbhFXPAA (ORCPT + 17 others); Thu, 24 Jun 2021 11:00:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231194AbhFXPAA (ORCPT ); Thu, 24 Jun 2021 11:00:00 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BEE0C061756 for ; Thu, 24 Jun 2021 07:57:40 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id j4so10766201lfc.8 for ; Thu, 24 Jun 2021 07:57:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zdxuO3FXcMYXnxkLpZHy8crKZag9SkX+E8b620Ln9pw=; b=cykGp7ubjyVx8XXCI0fgrRViUFGxjm6cjAzX0svOBQMbugUbJivFvBvyN57aLUv1+S 4iUG6X23ACy2rtX2bKN3M7iFaopOh7h2MJhDkeYhseKGTBH6A4Fe1rUCqmFXKwqvA7H4 4PWbLJF2nECpLfDa94DcQCqbxZo2Q1t9UP1sur5sgYhPN5PI5tnU3DL/P7jmTuxDcQ1i XdztqWdsz2UyPgniZT0IRdNwEAb5Lt6ti2BvAhZc7QaHqetdRysMXMreyRJGAG+W1LY2 +G7kwRlcrSiQnsl9PE47939+Neyn8DLrf9/Flboc42u0VqIXE5oKSSIeQb66px1mCM3V UoFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zdxuO3FXcMYXnxkLpZHy8crKZag9SkX+E8b620Ln9pw=; b=STfDaWXJEzTFEB7F8m/HoAl0rSZq0hHG5wvNE5Z9WIhto8pWo9EyBbRKL8u7eNsxrO 4nDX3EddRz9cIE7cBxenwg7hTKn31x/IVnQ2QvD3olOJrCcyPWZUAAtslnBBAI0w0Gem ES0l25eHcHb17+lSwqcyDAQC9Altqy3SmgZCkgVrHfpkdrJpAzFp9ie3vqqrcqy/JGa5 knF7Jqd3Z1XaCcOPX62heGzupvjCLpipMtFgW94+OTA1NFRjL/aB+kMAZ8yLi5JrJKEl pF0b3N9Wq8pMRhtZWIiX03hIDDh1ok8bFGOwsv5U+whkVaA890qxVsvs/J/HGmiy4uUs W2qQ== X-Gm-Message-State: AOAM531GYty3kv/Uy9ZlVXB3+PJIwWdYoHfJsQWT6U4eIgXiz7QBs6xg YdrK1wEgKaT953EyW/dAEmWI9Q== X-Received: by 2002:ac2:597a:: with SMTP id h26mr4194874lfp.406.1624546658871; Thu, 24 Jun 2021 07:57:38 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id e17sm306329ljn.125.2021.06.24.07.57.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Jun 2021 07:57:38 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 01/17] drm/msm/dpu: move LUT levels out of QOS config Date: Thu, 24 Jun 2021 17:57:17 +0300 Message-Id: <20210624145733.2561992-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210624145733.2561992-1-dmitry.baryshkov@linaro.org> References: <20210624145733.2561992-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org LUT levels are setup outside of setup_qos_ctrl, so remove them from the struct dpu_hw_pipe_qos_cfg. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 15 ++++++++------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 16 ++++++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 17 ++++++----------- 3 files changed, 20 insertions(+), 28 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 69eed7932486..cbafb61404d0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -569,19 +569,20 @@ static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum } static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_qos_cfg *cfg) + u32 danger_lut, + u32 safe_lut) { u32 idx; if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) return; - DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, cfg->danger_lut); - DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, cfg->safe_lut); + DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, danger_lut); + DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut); } static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_qos_cfg *cfg) + u64 creq_lut) { u32 idx; @@ -589,11 +590,11 @@ static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx, return; if (ctx->cap && test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features)) { - DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, cfg->creq_lut); + DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, creq_lut); DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx, - cfg->creq_lut >> 32); + creq_lut >> 32); } else { - DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, cfg->creq_lut); + DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, creq_lut); } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index fdfd4b46e2c6..27263bc1a1ef 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -166,18 +166,12 @@ struct dpu_hw_pipe_cfg { /** * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration - * @danger_lut: LUT for generate danger level based on fill level - * @safe_lut: LUT for generate safe level based on fill level - * @creq_lut: LUT for generate creq level based on fill level * @creq_vblank: creq value generated to vbif during vertical blanking * @danger_vblank: danger value generated during vertical blanking * @vblank_en: enable creq_vblank and danger_vblank during vblank * @danger_safe_en: enable danger safe generation */ struct dpu_hw_pipe_qos_cfg { - u32 danger_lut; - u32 safe_lut; - u64 creq_lut; u32 creq_vblank; u32 danger_vblank; bool vblank_en; @@ -302,20 +296,22 @@ struct dpu_hw_sspp_ops { /** * setup_danger_safe_lut - setup danger safe LUTs * @ctx: Pointer to pipe context - * @cfg: Pointer to pipe QoS configuration + * @danger_lut: LUT for generate danger level based on fill level + * @safe_lut: LUT for generate safe level based on fill level * */ void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_qos_cfg *cfg); + u32 danger_lut, + u32 safe_lut); /** * setup_creq_lut - setup CREQ LUT * @ctx: Pointer to pipe context - * @cfg: Pointer to pipe QoS configuration + * @creq_lut: LUT for generate creq level based on fill level * */ void (*setup_creq_lut)(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_qos_cfg *cfg); + u64 creq_lut); /** * setup_qos_ctrl - setup QoS control diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index ec4a6f04394a..1e2c53a3f47b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -348,8 +348,6 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, qos_lut = _dpu_plane_get_qos_lut( &pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl); - pdpu->pipe_qos_cfg.creq_lut = qos_lut; - trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0, pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage); @@ -359,7 +357,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, fmt ? (char *)&fmt->base.pixel_format : NULL, pdpu->is_rt_pipe, total_fl, qos_lut); - pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, &pdpu->pipe_qos_cfg); + pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut); } /** @@ -397,24 +395,21 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, } } - pdpu->pipe_qos_cfg.danger_lut = danger_lut; - pdpu->pipe_qos_cfg.safe_lut = safe_lut; - trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0, (fmt) ? fmt->fetch_mode : 0, - pdpu->pipe_qos_cfg.danger_lut, - pdpu->pipe_qos_cfg.safe_lut); + danger_lut, + safe_lut); DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", pdpu->pipe - SSPP_VIG0, fmt ? (char *)&fmt->base.pixel_format : NULL, fmt ? fmt->fetch_mode : -1, - pdpu->pipe_qos_cfg.danger_lut, - pdpu->pipe_qos_cfg.safe_lut); + danger_lut, + safe_lut); pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw, - &pdpu->pipe_qos_cfg); + danger_lut, safe_lut); } /**