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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id m13sm6259264iob.35.2021.06.21.10.56.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Jun 2021 10:56:32 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: robh+dt@kernel.org, angelogioacchino.delregno@somainline.org, jamipkettunen@gmail.com, bjorn.andersson@linaro.org, agross@kernel.org, elder@kernel.org, linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/6] net: ipa: inter-EE interrupts aren't always available Date: Mon, 21 Jun 2021 12:56:23 -0500 Message-Id: <20210621175627.238474-3-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210621175627.238474-1-elder@linaro.org> References: <20210621175627.238474-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GSI inter-EE interrupts are not supported prior to IPA v3.5. Don't attempt to initialize them in gsi_irq_setup() for hardware that does not support them. Originally proposed by AngeloGioacchino Del Regno. Link: https://lore.kernel.org/netdev/20210211175015.200772-4-angelogioacchino.delregno@somainline.org Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 13 ++++++++++--- drivers/net/ipa/gsi_reg.h | 3 ++- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index e374079603cf7..efd826e508bce 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -210,9 +210,16 @@ static void gsi_irq_setup(struct gsi *gsi) iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); - /* The inter-EE registers are in the non-adjusted address range */ - iowrite32(0, gsi->virt_raw + GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET); - iowrite32(0, gsi->virt_raw + GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET); + /* The inter-EE interrupts are not supported for IPA v3.0-v3.1 */ + if (gsi->version > IPA_VERSION_3_1) { + u32 offset; + + /* These registers are in the non-adjusted address range */ + offset = GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET; + iowrite32(0, gsi->virt_raw + offset); + offset = GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET; + iowrite32(0, gsi->virt_raw + offset); + } iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); } diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index cb42c5ae86fa2..bf9593d9eaead 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -52,7 +52,8 @@ */ #define GSI_EE_REG_ADJUST 0x0000d000 /* IPA v4.5+ */ -/* The two inter-EE IRQ register offsets are relative to gsi->virt_raw */ +/* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */ + #define GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET \ GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP) #define GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(ee) \