| Message ID | 20210617222029.463045-3-dmitry.baryshkov@linaro.org |
|---|---|
| State | Accepted |
| Commit | 6087623e7c904de4c8ff48f78dc70cc05ddb8e40 |
| Headers | show |
| Series | drm/msm/dpu: merge dpu_core_irq into dpu_hw_interrupts | expand |
On 2021-06-17 15:20, Dmitry Baryshkov wrote: > We already clear the IRQ status register before processing IRQs, so do > not clear the register again. Especially do not clear the IRQ status > _after_ processing the IRQ as this way we can loose the event. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> > --- > .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 17 ----------------- > 1 file changed, 17 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > index 2437b0c7c073..28e9b0d448db 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > @@ -120,21 +120,6 @@ static const struct dpu_intr_reg dpu_intr_set[] = > { > #define DPU_IRQ_REG(irq_idx) (irq_idx / 32) > #define DPU_IRQ_MASK(irq_idx) (BIT(irq_idx % 32)) > > -static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr > *intr, > - int irq_idx) > -{ > - int reg_idx; > - > - if (!intr) > - return; > - > - reg_idx = DPU_IRQ_REG(irq_idx); > - DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, > DPU_IRQ_MASK(irq_idx)); > - > - /* ensure register writes go through */ > - wmb(); > -} > - > /** > * dpu_core_irq_callback_handler - dispatch core interrupts > * @arg: private data of callback handler > @@ -203,8 +188,6 @@ irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms) > > dpu_core_irq_callback_handler(dpu_kms, irq_idx); > > - dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx); > - > /* > * When callback finish, clear the irq_status > * with the matching mask. Once irq_status
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 2437b0c7c073..28e9b0d448db 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -120,21 +120,6 @@ static const struct dpu_intr_reg dpu_intr_set[] = { #define DPU_IRQ_REG(irq_idx) (irq_idx / 32) #define DPU_IRQ_MASK(irq_idx) (BIT(irq_idx % 32)) -static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr, - int irq_idx) -{ - int reg_idx; - - if (!intr) - return; - - reg_idx = DPU_IRQ_REG(irq_idx); - DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_IRQ_MASK(irq_idx)); - - /* ensure register writes go through */ - wmb(); -} - /** * dpu_core_irq_callback_handler - dispatch core interrupts * @arg: private data of callback handler @@ -203,8 +188,6 @@ irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms) dpu_core_irq_callback_handler(dpu_kms, irq_idx); - dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx); - /* * When callback finish, clear the irq_status * with the matching mask. Once irq_status
We already clear the IRQ status register before processing IRQs, so do not clear the register again. Especially do not clear the IRQ status _after_ processing the IRQ as this way we can loose the event. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 17 ----------------- 1 file changed, 17 deletions(-) -- 2.30.2