From patchwork Tue May 25 13:13:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 447186 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp4258612jac; Tue, 25 May 2021 06:13:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyAfAjFQdHb9u0XWBtphygyJuxhLkIBVNOUpeETfU2Ft86sPs+Zd/EIdyrzA00hWDnEX5M0 X-Received: by 2002:aa7:d30d:: with SMTP id p13mr3678807edq.46.1621948409564; Tue, 25 May 2021 06:13:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621948409; cv=none; d=google.com; s=arc-20160816; b=wM7X3/bWSbVPfIBYXUc6ZueVvNu2aFpqRwu1vMgg33/WkRSqhbc6KOMQaZcYNTy+qz JdRrgxXYclon/wi300t96e8XW/FpzHMuaIMpisF3BZYfdIDB9+ZUiW2dhmdlK3DV2XPj vPHRW7C+lNRyC+qymhv4NNumwyFjB5/Gp4Cd7wuvDFnGH0yYgQ6UIQfgssBtsD2BOKbJ Rf6rZkdUMPqrPW95OGRP6dpuvwo6yOk0Om86RwB/5xJvktY0ffSFcCiMKzj5/Ts5VRyF I7MLSUGWeumfqYmOe399sZ32Q/ZQ0KZpoPCxgSwr6bGbWKKYA5ycyyWu3dLR3UKRYBqz Uttg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VWoFKEoGtTOuTzP0C2jwUTGuOWcUxql2hy1byMH9TIU=; b=DobQzi8GiSelDi1lmtV+1rYRSSCkzNRvTcw/eH2T6oE1LpJFp1jLs6ARMKpBPGYuyJ tKSzC40QOQLU+bhOTUcHIekxm1geoiqIsfJnwJWIY20BW83z2LHgnSywo89/oh37xddI PzLY0IZL+Stq+JMP79hBfc/B1vQfjjta1BWLz8Njpmbb+8ZKqIff6AEGqm1ESfxWOEwx DYGjokj+yqWDXt6g2lf6uI2TsUqY56LpCKG3zCzAerTZviJ5frFxrzQpfw5jJJiBYfDG /J//h1+3yYE2AT/Vd8iobXENGBZ6xs2wEboTWSJs4y76kcgrQj2bB74JhTLcEYi8xJcZ QTVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hfkwFnBM; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id hh4si15556805ejb.79.2021.05.25.06.13.29; Tue, 25 May 2021 06:13:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hfkwFnBM; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233150AbhEYNOz (ORCPT + 17 others); Tue, 25 May 2021 09:14:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233151AbhEYNOy (ORCPT ); Tue, 25 May 2021 09:14:54 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A38D5C061756 for ; Tue, 25 May 2021 06:13:24 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id f30so8996311lfj.1 for ; Tue, 25 May 2021 06:13:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VWoFKEoGtTOuTzP0C2jwUTGuOWcUxql2hy1byMH9TIU=; b=hfkwFnBMrceotvW547bghRykcjmWgmpbSNKji+seAYyqhsPfjwd1te1nef9J+lxUPR pFykXWcZzeLSq4oU4lIbzBj34/wvFpVyG8PWZSk/Om8HBGm8Q5cWCvKElCTKhDUTNamc S8HXlkTHphuRjPj1ZQkjgcpqBalZg7WmsOZ1AaRnlwiG/FW/R9NBhHYOupvHS01jcB37 oUTru/zXUKKzMA9hw6SNiYmydFnfG2CgyPgXW5jp71zTkttfyxZOn9fYMRYD51pScoOE 3Ldc/MOZ0XYDNehaWwaOUWamDBhlOqZh656kmO9Ncl+J383cJSIWMSCMBz0wBifcvbSY XyEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VWoFKEoGtTOuTzP0C2jwUTGuOWcUxql2hy1byMH9TIU=; b=H2SmqU5Pkn0LMWazH2+Yu3TVzJA39zfCueqMgy57s65g2sn2Yjw0hRHHysSeK2jPiJ i4tICEzC8InQlDYWqdYbqsRvn33mzKXxxag+0naYMgNjA/Hqt7RVE+k1BwvUhXPjy+RK Z++Az5g9KhManBboFSvM0ctPRKWuEP6Ken2gfIOsJnGw9KkRF6UQ5+d9we3ZHcScag4t aUHM/RpEEsdY5s2fPBVbAdICXM9IyBXrL3xwPFwh50hqqtUE+Df0IwNzMZEWhNMAIsqU EJTPq8q0iuMvMo637MmLvtNtuVRexbyMeiR2/LPBpp/nI6z8fDQHv9WjNTFTWW5Wv0zQ knPA== X-Gm-Message-State: AOAM5306ovRvNvKCMob2k1bNUPWvVXufpm26r7mp1jBeceu0u0w4luxg /ICoIgMd/XJZAeP9b6/QjOU9EQ== X-Received: by 2002:a05:6512:209:: with SMTP id a9mr14628411lfo.219.1621948403005; Tue, 25 May 2021 06:13:23 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id t20sm2101108lji.53.2021.05.25.06.13.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 May 2021 06:13:22 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, James Willcox Subject: [PATCH 6/7] drm/msm/mdp5: add perf blocks for holding fudge factors Date: Tue, 25 May 2021 16:13:15 +0300 Message-Id: <20210525131316.3117809-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210525131316.3117809-1-dmitry.baryshkov@linaro.org> References: <20210525131316.3117809-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: James Willcox Prior downstream kernels had "fudge factors" in devicetree which would be applied to things like interconnect bandwidth calculations. Bring some of those values back here. Signed-off-by: James Willcox [DB: changed _ff to _inefficiency, fixed patch description] Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 35 ++++++++++++++++++++++++ drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h | 7 +++++ 2 files changed, 42 insertions(+) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c index 94ce62a26daf..9741544ffc35 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c @@ -95,6 +95,11 @@ static const struct mdp5_cfg_hw msm8x74v1_config = { [3] = INTF_HDMI, }, }, + .perf = { + .ab_inefficiency = 200, + .ib_inefficiency = 120, + .clk_inefficiency = 125 + }, .max_clk = 200000000, }; @@ -177,6 +182,11 @@ static const struct mdp5_cfg_hw msm8x74v2_config = { [3] = INTF_HDMI, }, }, + .perf = { + .ab_inefficiency = 200, + .ib_inefficiency = 120, + .clk_inefficiency = 125 + }, .max_clk = 320000000, }; @@ -272,6 +282,11 @@ static const struct mdp5_cfg_hw apq8084_config = { [3] = INTF_HDMI, }, }, + .perf = { + .ab_inefficiency = 200, + .ib_inefficiency = 120, + .clk_inefficiency = 105 + }, .max_clk = 320000000, }; @@ -339,6 +354,11 @@ static const struct mdp5_cfg_hw msm8x16_config = { [1] = INTF_DSI, }, }, + .perf = { + .ab_inefficiency = 100, + .ib_inefficiency = 200, + .clk_inefficiency = 105 + }, .max_clk = 320000000, }; @@ -414,6 +434,11 @@ static const struct mdp5_cfg_hw msm8x36_config = { [2] = INTF_DSI, }, }, + .perf = { + .ab_inefficiency = 100, + .ib_inefficiency = 200, + .clk_inefficiency = 105 + }, .max_clk = 366670000, }; @@ -509,6 +534,11 @@ static const struct mdp5_cfg_hw msm8x94_config = { [3] = INTF_HDMI, }, }, + .perf = { + .ab_inefficiency = 100, + .ib_inefficiency = 100, + .clk_inefficiency = 105 + }, .max_clk = 400000000, }; @@ -617,6 +647,11 @@ static const struct mdp5_cfg_hw msm8x96_config = { [3] = INTF_HDMI, }, }, + .perf = { + .ab_inefficiency = 100, + .ib_inefficiency = 200, + .clk_inefficiency = 105 + }, .max_clk = 412500000, }; diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h index 1c50d01f15f5..6b03d7899309 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h @@ -76,6 +76,12 @@ struct mdp5_intf_block { u32 connect[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */ }; +struct mdp5_perf_block { + u32 ab_inefficiency; + u32 ib_inefficiency; + u32 clk_inefficiency; +}; + struct mdp5_cfg_hw { char *name; @@ -93,6 +99,7 @@ struct mdp5_cfg_hw { struct mdp5_sub_block dsc; struct mdp5_sub_block cdm; struct mdp5_intf_block intf; + struct mdp5_perf_block perf; uint32_t max_clk; };