From patchwork Fri May 21 12:49:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 445947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EB28C43462 for ; Fri, 21 May 2021 12:51:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1623E613D9 for ; Fri, 21 May 2021 12:51:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235046AbhEUMw3 (ORCPT ); Fri, 21 May 2021 08:52:29 -0400 Received: from mail.kernel.org ([198.145.29.99]:34214 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234858AbhEUMwL (ORCPT ); Fri, 21 May 2021 08:52:11 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 4579D613D8; Fri, 21 May 2021 12:50:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601448; bh=0XahmhIFMEbevuz651JK1SuRalOKFeJShM5ZS9hUNOw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p+b1dMuLcyV319Bhe3jSEigdayqKsFhF//ypqJCP+tluFH8ZmM8eq2gAlvlHrHLhG DM7rm48oYDW1OO42JBNc98oyZmjUCZwM3wiAVVBGBry1AAAwK7CK9NkoHxqmQGCbel MNp2RrXN7BjXR4PEqdURurAdn5zsJv5d5aUJzfjM/l2gHWboplc1+q3Bjl/4clH1tH 98w47KacMrvjiyAqlv4lewKUCj+5utIiFXscIPz/fBLWV/QsIeLUgEhp1WyMuaG60J L1vzriacLSu4IPLeYspBAA3IrFfoDsNdexO/Gii5yGjsCzMUzCLRjNeg5C/4/uPiQB cV3CdAQkUn3AQ== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [RFC PATCH 08/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl Date: Fri, 21 May 2021 18:19:40 +0530 Message-Id: <20210521124946.3617862-12-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Later gens of hardware have DSC bits moved to hw_ctl, so configure these bits so that DSC would work there as well Signed-off-by: Vinod Koul --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 2d4645e01ebf..aeea6add61ee 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -25,6 +25,8 @@ #define CTL_MERGE_3D_ACTIVE 0x0E4 #define CTL_INTF_ACTIVE 0x0F4 #define CTL_MERGE_3D_FLUSH 0x100 +#define CTL_DSC_ACTIVE 0x0E8 +#define CTL_DSC_FLUSH 0x104 #define CTL_INTF_FLUSH 0x110 #define CTL_INTF_MASTER 0x134 #define CTL_FETCH_PIPE_ACTIVE 0x0FC @@ -34,6 +36,7 @@ #define DPU_REG_RESET_TIMEOUT_US 2000 #define MERGE_3D_IDX 23 +#define DSC_IDX 22 #define INTF_IDX 31 #define CTL_INVALID_BIT 0xffff @@ -120,6 +123,7 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) { + DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, BIT(0) | BIT(1) | BIT(2) | BIT(3)); if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX)) DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH, @@ -128,7 +132,7 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH, ctx->pending_intf_flush_mask); - DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask | BIT(DSC_IDX)); } static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx) @@ -507,6 +511,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->merge_3d) DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0)); + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, BIT(0) | BIT(1) | BIT(2) | BIT(3)); } static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,