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[23.128.96.18]) by mx.google.com with ESMTP id j11si13543185pfc.134.2021.04.11.17.10.03; Sun, 11 Apr 2021 17:10:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fzyiZDWv; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235740AbhDLAKT (ORCPT + 16 others); Sun, 11 Apr 2021 20:10:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235095AbhDLAKT (ORCPT ); Sun, 11 Apr 2021 20:10:19 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BABD1C061574 for ; Sun, 11 Apr 2021 17:10:00 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id b4so18503200lfi.6 for ; Sun, 11 Apr 2021 17:10:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B8QbNP1RBmcdaj/DpJzyvoSd4xk2B3m0lm5h+jBxVxQ=; b=fzyiZDWvLxVbDBEdU0s1nZkCWTfeqcfn9CqYqT/T8Zn6VoPCeVX4UsHfkyZjwkp2Ma xEkolh1DgVCVvj+/HtkChpSDub+p8y7dzIiQE9BvYEv9XFu4JrJzsSjZRWx7R2i8Bh3J 7tRx06h+isNYk9ooTb5Xg9Zy5I/xIFKHtklaHHcrlLbjPRwHe2j6SXBtla7s9ZiQebMD DHTLLsn1UWNA1fcWTPS9aEWHnlXtX8YhpUNWC96w50lXgt53SxPDttyxRbiWkh1PgCU+ h3tgnGmoJfU2TjkBEUVldbYL0ZlNsRf/Q3Rmk9U1oaYBqml4RV4vVSrGd+926EwtA9kO 87KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B8QbNP1RBmcdaj/DpJzyvoSd4xk2B3m0lm5h+jBxVxQ=; b=i8KJy0pJY2iRHXBgvXr7bhS8M9sB1KDYMtZ8aKHwdlpa4m8Z5eyQKs2z79L2cX6pL0 ozMn3HykhILKqK4jfqGFjq+wvuQBAn0W7EBYUUFtgvzyjM0gpQB64nvQgOJDm6OsPKQI Yz52OqBQZpWFJ9rPVMEW4wfC7cibpWu/y+kVe+RAYwcH74z6CYbLpkXr4UdO3ZuKAsTv qa9frt504QyTvc9NxmAZ4Ts//GK+dA64uJ31bCNSp2N9WyIzS61pk5Im3YuXEnIcwd5q xKXGdsnTnV016GOJr+nL13b/jWJbamUqbQVpLn/umUhKhx3tnS7/eo/WiQFD76Nh/BJB uQbA== X-Gm-Message-State: AOAM533dYukxlxfrIiKuJXK3LuIJcAM1XyTtf1EiGoGnX6GKymKtuRV7 F2pKkilT88T41hNwMzDIAOgzPw== X-Received: by 2002:a05:6512:6cd:: with SMTP id u13mr17304963lff.326.1618186199210; Sun, 11 Apr 2021 17:09:59 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s22sm2307212ljd.28.2021.04.11.17.09.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Apr 2021 17:09:58 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v1 2/3] drm/msm/dpu: hw_intr: always call dpu_hw_intr_clear_intr_status_nolock Date: Mon, 12 Apr 2021 03:09:53 +0300 Message-Id: <20210412000954.2049141-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210412000954.2049141-1-dmitry.baryshkov@linaro.org> References: <20210412000954.2049141-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Always call dpu_hw_intr_clear_intr_status_nolock() from the dpu_hw_intr_dispatch_irqs(). This simplifies the callback function (which call clears the interrupts anyway) and enforces clearing the hw interrupt status. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 9 ----- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 39 +++++++++---------- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 9 ----- 3 files changed, 18 insertions(+), 39 deletions(-) -- 2.30.2 Reviewed-by: Bjorn Andersson diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c index 54b34746a587..fd11a2aeab6c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c @@ -41,15 +41,6 @@ static void dpu_core_irq_callback_handler(void *arg, int irq_idx) if (cb->func) cb->func(cb->arg, irq_idx); spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags); - - /* - * Clear pending interrupt status in HW. - * NOTE: dpu_core_irq_callback_handler is protected by top-level - * spinlock, so it is safe to clear any interrupt status here. - */ - dpu_kms->hw_intr->ops.clear_intr_status_nolock( - dpu_kms->hw_intr, - irq_idx); } int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index cf9bfd45aa59..8bd22e060437 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -1362,6 +1362,22 @@ static int dpu_hw_intr_irqidx_lookup(struct dpu_hw_intr *intr, return -EINVAL; } +static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr, + int irq_idx) +{ + int reg_idx; + + if (!intr) + return; + + reg_idx = dpu_irq_map[irq_idx].reg_idx; + DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, + dpu_irq_map[irq_idx].irq_mask); + + /* ensure register writes go through */ + wmb(); +} + static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, void (*cbfunc)(void *, int), void *arg) @@ -1430,9 +1446,8 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, */ if (cbfunc) cbfunc(arg, irq_idx); - else - intr->ops.clear_intr_status_nolock( - intr, irq_idx); + + dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx); /* * When callback finish, clear the irq_status @@ -1597,23 +1612,6 @@ static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr) return 0; } - -static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr, - int irq_idx) -{ - int reg_idx; - - if (!intr) - return; - - reg_idx = dpu_irq_map[irq_idx].reg_idx; - DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, - dpu_irq_map[irq_idx].irq_mask); - - /* ensure register writes go through */ - wmb(); -} - static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, int irq_idx, bool clear) { @@ -1655,7 +1653,6 @@ static void __setup_intr_ops(struct dpu_hw_intr_ops *ops) ops->dispatch_irqs = dpu_hw_intr_dispatch_irq; ops->clear_all_irqs = dpu_hw_intr_clear_irqs; ops->disable_all_irqs = dpu_hw_intr_disable_irqs; - ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock; ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index 5a1c304ba93f..5bade5637ecc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -142,15 +142,6 @@ struct dpu_hw_intr_ops { void (*cbfunc)(void *arg, int irq_idx), void *arg); - /** - * clear_intr_status_nolock() - clears the HW interrupts without lock - * @intr: HW interrupt handle - * @irq_idx: Lookup irq index return from irq_idx_lookup - */ - void (*clear_intr_status_nolock)( - struct dpu_hw_intr *intr, - int irq_idx); - /** * get_interrupt_status - Gets HW interrupt status, and clear if set, * based on given lookup IRQ index.