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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id e6sm1303691iom.2.2021.04.09.06.44.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Apr 2021 06:44:11 -0700 (PDT) From: Alex Elder To: bjorn.andersson@linaro.org, agross@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] clk: qcom: rpmh: add support for SDX55 rpmh IPA clock Date: Fri, 9 Apr 2021 08:44:07 -0500 Message-Id: <20210409134407.841137-1-elder@linaro.org> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The IPA core clock is required for SDX55. Define it. Signed-off-by: Alex Elder --- drivers/clk/qcom/clk-rpmh.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.27.0 Tested-by: Manivannan Sadhasivam Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index c623ce9004063..552d1cbfea4c0 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -380,6 +380,7 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = { DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1); DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1); DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0"); +DEFINE_CLK_RPMH_BCM(sdx55, ipa, "IP0"); static struct clk_hw *sdx55_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, @@ -389,6 +390,7 @@ static struct clk_hw *sdx55_rpmh_clocks[] = { [RPMH_RF_CLK2] = &sdx55_rf_clk2.hw, [RPMH_RF_CLK2_A] = &sdx55_rf_clk2_ao.hw, [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw, + [RPMH_IPA_CLK] = &sdx55_ipa.hw, }; static const struct clk_rpmh_desc clk_rpmh_sdx55 = {