diff mbox series

[21/21] drm/msm/dpu: call hw_intr ops directly

Message ID 20210324150024.2768215-22-dmitry.baryshkov@linaro.org
State New
Headers show
Series None | expand

Commit Message

Dmitry Baryshkov March 24, 2021, 3 p.m. UTC 
Replace dpu_hw_intr callbacks with direct functions calls.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c  |  27 ++-
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c |  36 ++--
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 180 +++++++++---------
 3 files changed, 111 insertions(+), 132 deletions(-)

Comments

kernel test robot March 24, 2021, 5:56 p.m. UTC | #1 
Hi Dmitry,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v5.12-rc4 next-20210324]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Dmitry-Baryshkov/drm-msm-dpu-cleanup-callbacks-resource-manager/20210324-230347
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 7acac4b3196caee5e21fb5ea53f8bc124e6a16fc
config: arm-defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/8f82b58643355f9e0d03c022b66e276c252e633a
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Dmitry-Baryshkov/drm-msm-dpu-cleanup-callbacks-resource-manager/20210324-230347
        git checkout 8f82b58643355f9e0d03c022b66e276c252e633a
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:889:5: warning: no previous prototype for 'dpu_hw_intr_disable_irq_nolock' [-Wmissing-prototypes]
     889 | int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
         |     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


vim +/dpu_hw_intr_disable_irq_nolock +889 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

   888	
 > 889	int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
   890	{
   891		int reg_idx;
   892		const struct dpu_intr_reg *reg;
   893		const struct dpu_irq_type *irq;
   894		const char *dbgstr = NULL;
   895		uint32_t cache_irq_mask;
   896	
   897		if (!intr)
   898			return -EINVAL;
   899	
   900		if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
   901			pr_err("invalid IRQ index: [%d]\n", irq_idx);
   902			return -EINVAL;
   903		}
   904	
   905		irq = &dpu_irq_map[irq_idx];
   906		reg_idx = irq->reg_idx;
   907		reg = &dpu_intr_set[reg_idx];
   908	
   909		cache_irq_mask = intr->cache_irq_mask[reg_idx];
   910		if ((cache_irq_mask & irq->irq_mask) == 0) {
   911			dbgstr = "DPU IRQ is already cleared:";
   912		} else {
   913			dbgstr = "DPU IRQ mask disable:";
   914	
   915			cache_irq_mask &= ~irq->irq_mask;
   916			/* Disable interrupts based on the new mask */
   917			DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
   918			/* Cleaning any pending interrupt */
   919			DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
   920	
   921			/* ensure register write goes through */
   922			wmb();
   923	
   924			intr->cache_irq_mask[reg_idx] = cache_irq_mask;
   925		}
   926	
   927		pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
   928				irq->irq_mask, cache_irq_mask);
   929	
   930		return 0;
   931	}
   932	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
kernel test robot March 24, 2021, 8:21 p.m. UTC | #2 
Hi Dmitry,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v5.12-rc4 next-20210324]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Dmitry-Baryshkov/drm-msm-dpu-cleanup-callbacks-resource-manager/20210324-230347
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 7acac4b3196caee5e21fb5ea53f8bc124e6a16fc
config: arm64-randconfig-r036-20210324 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project a4fb88669cd98db6fef7dcac88e3ec425d40c00d)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        # https://github.com/0day-ci/linux/commit/8f82b58643355f9e0d03c022b66e276c252e633a
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Dmitry-Baryshkov/drm-msm-dpu-cleanup-callbacks-resource-manager/20210324-230347
        git checkout 8f82b58643355f9e0d03c022b66e276c252e633a
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:889:5: warning: no previous prototype for function 'dpu_hw_intr_disable_irq_nolock' [-Wmissing-prototypes]
   int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
       ^
   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:889:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
   ^
   static 
   1 warning generated.


vim +/dpu_hw_intr_disable_irq_nolock +889 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

   888	
 > 889	int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
   890	{
   891		int reg_idx;
   892		const struct dpu_intr_reg *reg;
   893		const struct dpu_irq_type *irq;
   894		const char *dbgstr = NULL;
   895		uint32_t cache_irq_mask;
   896	
   897		if (!intr)
   898			return -EINVAL;
   899	
   900		if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
   901			pr_err("invalid IRQ index: [%d]\n", irq_idx);
   902			return -EINVAL;
   903		}
   904	
   905		irq = &dpu_irq_map[irq_idx];
   906		reg_idx = irq->reg_idx;
   907		reg = &dpu_intr_set[reg_idx];
   908	
   909		cache_irq_mask = intr->cache_irq_mask[reg_idx];
   910		if ((cache_irq_mask & irq->irq_mask) == 0) {
   911			dbgstr = "DPU IRQ is already cleared:";
   912		} else {
   913			dbgstr = "DPU IRQ mask disable:";
   914	
   915			cache_irq_mask &= ~irq->irq_mask;
   916			/* Disable interrupts based on the new mask */
   917			DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
   918			/* Cleaning any pending interrupt */
   919			DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
   920	
   921			/* ensure register write goes through */
   922			wmb();
   923	
   924			intr->cache_irq_mask[reg_idx] = cache_irq_mask;
   925		}
   926	
   927		pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
   928				irq->irq_mask, cache_irq_mask);
   929	
   930		return 0;
   931	}
   932	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index 84ea09d9692f..57c5485c0213 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -47,7 +47,7 @@  static void dpu_core_irq_callback_handler(void *arg, int irq_idx)
 	 * NOTE: dpu_core_irq_callback_handler is protected by top-level
 	 *       spinlock, so it is safe to clear any interrupt status here.
 	 */
-	dpu_kms->hw_intr->ops.clear_intr_status_nolock(
+	dpu_hw_intr_clear_intr_status_nolock(
 			dpu_kms->hw_intr,
 			irq_idx);
 }
@@ -55,10 +55,10 @@  static void dpu_core_irq_callback_handler(void *arg, int irq_idx)
 int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms,
 		enum dpu_intr_type intr_type, u32 instance_idx)
 {
-	if (!dpu_kms->hw_intr || !dpu_kms->hw_intr->ops.irq_idx_lookup)
+	if (!dpu_kms->hw_intr)
 		return -EINVAL;
 
-	return dpu_kms->hw_intr->ops.irq_idx_lookup(intr_type,
+	return dpu_hw_intr_irq_idx_lookup(intr_type,
 			instance_idx);
 }
 
@@ -89,7 +89,7 @@  static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx)
 	trace_dpu_core_irq_enable_idx(irq_idx, enable_count);
 
 	if (atomic_inc_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 1) {
-		ret = dpu_kms->hw_intr->ops.enable_irq(
+		ret = dpu_hw_intr_enable_irq(
 				dpu_kms->hw_intr,
 				irq_idx);
 		if (ret)
@@ -152,7 +152,7 @@  static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx)
 	trace_dpu_core_irq_disable_idx(irq_idx, enable_count);
 
 	if (atomic_dec_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 0) {
-		ret = dpu_kms->hw_intr->ops.disable_irq(
+		ret = dpu_hw_intr_disable_irq(
 				dpu_kms->hw_intr,
 				irq_idx);
 		if (ret)
@@ -185,8 +185,7 @@  int dpu_core_irq_disable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count)
 
 u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx, bool clear)
 {
-	if (!dpu_kms->hw_intr ||
-			!dpu_kms->hw_intr->ops.get_interrupt_status)
+	if (!dpu_kms->hw_intr)
 		return 0;
 
 	if (irq_idx < 0) {
@@ -195,7 +194,7 @@  u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx, bool clear)
 		return 0;
 	}
 
-	return dpu_kms->hw_intr->ops.get_interrupt_status(dpu_kms->hw_intr,
+	return dpu_hw_intr_get_interrupt_status(dpu_kms->hw_intr,
 			irq_idx, clear);
 }
 
@@ -273,18 +272,18 @@  int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms, int irq_idx,
 
 static void dpu_clear_all_irqs(struct dpu_kms *dpu_kms)
 {
-	if (!dpu_kms->hw_intr || !dpu_kms->hw_intr->ops.clear_all_irqs)
+	if (!dpu_kms->hw_intr)
 		return;
 
-	dpu_kms->hw_intr->ops.clear_all_irqs(dpu_kms->hw_intr);
+	dpu_hw_intr_clear_all_irqs(dpu_kms->hw_intr);
 }
 
 static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)
 {
-	if (!dpu_kms->hw_intr || !dpu_kms->hw_intr->ops.disable_all_irqs)
+	if (!dpu_kms->hw_intr)
 		return;
 
-	dpu_kms->hw_intr->ops.disable_all_irqs(dpu_kms->hw_intr);
+	dpu_hw_intr_disable_all_irqs(dpu_kms->hw_intr);
 }
 
 #ifdef CONFIG_DEBUG_FS
@@ -383,7 +382,7 @@  irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms)
 	 * Individual interrupt status bit will only get stored if it
 	 * is enabled.
 	 */
-	dpu_kms->hw_intr->ops.get_interrupt_statuses(dpu_kms->hw_intr);
+	dpu_hw_intr_get_interrupt_statuses(dpu_kms->hw_intr);
 
 	/*
 	 * Dispatch to HW driver to handle interrupt lookup that is being
@@ -393,7 +392,7 @@  irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms)
 	 * callback, and do the interrupt status clearing once the registered
 	 * callback is finished.
 	 */
-	dpu_kms->hw_intr->ops.dispatch_irqs(
+	dpu_hw_intr_dispatch_irqs(
 			dpu_kms->hw_intr,
 			dpu_core_irq_callback_handler,
 			dpu_kms);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 5c521de71567..a2db9807b41d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -755,7 +755,7 @@  static const struct dpu_irq_type dpu_irq_map[] = {
 	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
 };
 
-static int dpu_hw_intr_irqidx_lookup(enum dpu_intr_type intr_type,
+int dpu_hw_intr_irq_idx_lookup(enum dpu_intr_type intr_type,
 		u32 instance_idx)
 {
 	int i;
@@ -771,7 +771,7 @@  static int dpu_hw_intr_irqidx_lookup(enum dpu_intr_type intr_type,
 	return -EINVAL;
 }
 
-static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
+void dpu_hw_intr_dispatch_irqs(struct dpu_hw_intr *intr,
 		void (*cbfunc)(void *, int),
 		void *arg)
 {
@@ -825,7 +825,7 @@  static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
 				if (cbfunc)
 					cbfunc(arg, irq_idx);
 				else
-					intr->ops.clear_intr_status_nolock(
+					dpu_hw_intr_clear_intr_status_nolock(
 							intr, irq_idx);
 
 				/*
@@ -839,7 +839,7 @@  static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
 	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
 }
 
-static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx)
+int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx)
 {
 	int reg_idx;
 	unsigned long irq_flags;
@@ -886,7 +886,7 @@  static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx)
 	return 0;
 }
 
-static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
+int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
 {
 	int reg_idx;
 	const struct dpu_intr_reg *reg;
@@ -930,7 +930,7 @@  static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
 	return 0;
 }
 
-static int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx)
+int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx)
 {
 	unsigned long irq_flags;
 
@@ -949,7 +949,7 @@  static int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx)
 	return 0;
 }
 
-static int dpu_hw_intr_clear_irqs(struct dpu_hw_intr *intr)
+int dpu_hw_intr_clear_all_irqs(struct dpu_hw_intr *intr)
 {
 	int i;
 
@@ -968,7 +968,7 @@  static int dpu_hw_intr_clear_irqs(struct dpu_hw_intr *intr)
 	return 0;
 }
 
-static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr)
+int dpu_hw_intr_disable_all_irqs(struct dpu_hw_intr *intr)
 {
 	int i;
 
@@ -987,7 +987,7 @@  static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr)
 	return 0;
 }
 
-static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr)
+void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr)
 {
 	int i;
 	u32 enable_mask;
@@ -1023,7 +1023,7 @@  static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr)
 	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
 }
 
-static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
+void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
 		int irq_idx)
 {
 	int reg_idx;
@@ -1039,7 +1039,7 @@  static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
 	wmb();
 }
 
-static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
+u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
 		int irq_idx, bool clear)
 {
 	int reg_idx;
@@ -1072,19 +1072,6 @@  static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
 	return intr_status;
 }
 
-static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)
-{
-	ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup;
-	ops->enable_irq = dpu_hw_intr_enable_irq;
-	ops->disable_irq = dpu_hw_intr_disable_irq;
-	ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
-	ops->clear_all_irqs = dpu_hw_intr_clear_irqs;
-	ops->disable_all_irqs = dpu_hw_intr_disable_irqs;
-	ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses;
-	ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock;
-	ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;
-}
-
 static void __intr_offset(struct dpu_mdss_cfg *m,
 		void __iomem *addr, struct dpu_hw_blk_reg_map *hw)
 {
@@ -1106,7 +1093,6 @@  struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
 		return ERR_PTR(-ENOMEM);
 
 	__intr_offset(m, addr, &intr->hw);
-	__setup_intr_ops(&intr->ops);
 
 	intr->irq_idx_tbl_size = ARRAY_SIZE(dpu_irq_map);
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index fc9c98617281..17b0f7a862a5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -77,99 +77,94 @@  enum dpu_intr_type {
 struct dpu_hw_intr;
 
 /**
- * Interrupt operations.
+ * dpu_hw_intr_irq_idx_lookup - Lookup IRQ index on the HW interrupt type
+ *                 Used for all irq related ops
+ * @intr_type:		Interrupt type defined in dpu_intr_type
+ * @instance_idx:	HW interrupt block instance
+ * @return:		irq_idx or -EINVAL for lookup fail
  */
-struct dpu_hw_intr_ops {
-	/**
-	 * irq_idx_lookup - Lookup IRQ index on the HW interrupt type
-	 *                 Used for all irq related ops
-	 * @intr_type:		Interrupt type defined in dpu_intr_type
-	 * @instance_idx:	HW interrupt block instance
-	 * @return:		irq_idx or -EINVAL for lookup fail
-	 */
-	int (*irq_idx_lookup)(
-			enum dpu_intr_type intr_type,
-			u32 instance_idx);
-
-	/**
-	 * enable_irq - Enable IRQ based on lookup IRQ index
-	 * @intr:	HW interrupt handle
-	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
-	 * @return:	0 for success, otherwise failure
-	 */
-	int (*enable_irq)(
-			struct dpu_hw_intr *intr,
-			int irq_idx);
-
-	/**
-	 * disable_irq - Disable IRQ based on lookup IRQ index
-	 * @intr:	HW interrupt handle
-	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
-	 * @return:	0 for success, otherwise failure
-	 */
-	int (*disable_irq)(
-			struct dpu_hw_intr *intr,
-			int irq_idx);
-
-	/**
-	 * clear_all_irqs - Clears all the interrupts (i.e. acknowledges
-	 *                  any asserted IRQs). Useful during reset.
-	 * @intr:	HW interrupt handle
-	 * @return:	0 for success, otherwise failure
-	 */
-	int (*clear_all_irqs)(
-			struct dpu_hw_intr *intr);
-
-	/**
-	 * disable_all_irqs - Disables all the interrupts. Useful during reset.
-	 * @intr:	HW interrupt handle
-	 * @return:	0 for success, otherwise failure
-	 */
-	int (*disable_all_irqs)(
-			struct dpu_hw_intr *intr);
-
-	/**
-	 * dispatch_irqs - IRQ dispatcher will call the given callback
-	 *                 function when a matching interrupt status bit is
-	 *                 found in the irq mapping table.
-	 * @intr:	HW interrupt handle
-	 * @cbfunc:	Callback function pointer
-	 * @arg:	Argument to pass back during callback
-	 */
-	void (*dispatch_irqs)(
-			struct dpu_hw_intr *intr,
-			void (*cbfunc)(void *arg, int irq_idx),
-			void *arg);
-
-	/**
-	 * get_interrupt_statuses - Gets and store value from all interrupt
-	 *                          status registers that are currently fired.
-	 * @intr:	HW interrupt handle
-	 */
-	void (*get_interrupt_statuses)(
-			struct dpu_hw_intr *intr);
-
-	/**
-	 * clear_intr_status_nolock() - clears the HW interrupts without lock
-	 * @intr:	HW interrupt handle
-	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
-	 */
-	void (*clear_intr_status_nolock)(
-			struct dpu_hw_intr *intr,
-			int irq_idx);
-
-	/**
-	 * get_interrupt_status - Gets HW interrupt status, and clear if set,
-	 *                        based on given lookup IRQ index.
-	 * @intr:	HW interrupt handle
-	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
-	 * @clear:	True to clear irq after read
-	 */
-	u32 (*get_interrupt_status)(
-			struct dpu_hw_intr *intr,
-			int irq_idx,
-			bool clear);
-};
+int dpu_hw_intr_irq_idx_lookup(
+		enum dpu_intr_type intr_type,
+		u32 instance_idx);
+
+/**
+ * dpu_hw_intr_enable_irq - Enable IRQ based on lookup IRQ index
+ * @intr:	HW interrupt handle
+ * @irq_idx:	Lookup irq index return from irq_idx_lookup
+ * @return:	0 for success, otherwise failure
+ */
+int dpu_hw_intr_enable_irq(
+		struct dpu_hw_intr *intr,
+		int irq_idx);
+
+/**
+ * dpu_hw_intr_disable_irq - Disable IRQ based on lookup IRQ index
+ * @intr:	HW interrupt handle
+ * @irq_idx:	Lookup irq index return from irq_idx_lookup
+ * @return:	0 for success, otherwise failure
+ */
+int dpu_hw_intr_disable_irq(
+		struct dpu_hw_intr *intr,
+		int irq_idx);
+
+/**
+ * dpu_hw_intr_clear_all_irqs - Clears all the interrupts (i.e. acknowledges
+ *                  any asserted IRQs). Useful during reset.
+ * @intr:	HW interrupt handle
+ * @return:	0 for success, otherwise failure
+ */
+int dpu_hw_intr_clear_all_irqs(
+		struct dpu_hw_intr *intr);
+
+/**
+ * dpu_hw_intr_disable_all_irqs - Disables all the interrupts. Useful during reset.
+ * @intr:	HW interrupt handle
+ * @return:	0 for success, otherwise failure
+ */
+int dpu_hw_intr_disable_all_irqs(
+		struct dpu_hw_intr *intr);
+
+/**
+ * dpu_hw_intr_dispatch_irqs - IRQ dispatcher will call the given callback
+ *                 function when a matching interrupt status bit is
+ *                 found in the irq mapping table.
+ * @intr:	HW interrupt handle
+ * @cbfunc:	Callback function pointer
+ * @arg:	Argument to pass back during callback
+ */
+void dpu_hw_intr_dispatch_irqs(
+		struct dpu_hw_intr *intr,
+		void dpu_hw_intr_cbfunc(void *arg, int irq_idx),
+		void *arg);
+
+/**
+ * dpu_hw_intr_get_interrupt_statuses - Gets and store value from all interrupt
+ *                          status registers that are currently fired.
+ * @intr:	HW interrupt handle
+ */
+void dpu_hw_intr_get_interrupt_statuses(
+		struct dpu_hw_intr *intr);
+
+/**
+ * dpu_hw_intr_clear_intr_status_nolock() - clears the HW interrupts without lock
+ * @intr:	HW interrupt handle
+ * @irq_idx:	Lookup irq index return from irq_idx_lookup
+ */
+void dpu_hw_intr_clear_intr_status_nolock(
+		struct dpu_hw_intr *intr,
+		int irq_idx);
+
+/**
+ * dpu_hw_intr_get_interrupt_status - Gets HW interrupt status, and clear if set,
+ *                        based on given lookup IRQ index.
+ * @intr:	HW interrupt handle
+ * @irq_idx:	Lookup irq index return from irq_idx_lookup
+ * @clear:	True to clear irq after read
+ */
+u32 dpu_hw_intr_get_interrupt_status(
+		struct dpu_hw_intr *intr,
+		int irq_idx,
+		bool clear);
 
 /**
  * struct dpu_hw_intr: hw interrupts handling data structure
@@ -182,7 +177,6 @@  struct dpu_hw_intr_ops {
  */
 struct dpu_hw_intr {
 	struct dpu_hw_blk_reg_map hw;
-	struct dpu_hw_intr_ops ops;
 	u32 *cache_irq_mask;
 	u32 *save_irq_status;
 	u32 irq_idx_tbl_size;