| Message ID | 20201126085705.48399-2-manivannan.sadhasivam@linaro.org |
|---|---|
| State | Accepted |
| Commit | ce22be4307b801b4e24773c6290dd913b751d436 |
| Headers | show |
| Series | Add NAND support for SDX55 | expand |
On Thu, 26 Nov 2020 14:27:04 +0530, Manivannan Sadhasivam wrote: > Qualcomm SDX55 uses QPIC NAND controller version 2.0.0 with BAM DMA > Engine. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt index 5c2fba4b30fe..a971db361678 100644 --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt @@ -8,6 +8,8 @@ Required properties: IPQ4019 SoC and it uses BAM DMA * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in IPQ8074 SoC and it uses BAM DMA + * "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in + SDX55 SoC and it uses BAM DMA - reg: MMIO address range - clocks: must contain core clock and always on clock
Qualcomm SDX55 uses QPIC NAND controller version 2.0.0 with BAM DMA Engine. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 2 ++ 1 file changed, 2 insertions(+) -- 2.25.1