From patchwork Thu Nov 26 07:21:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 332923 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp1091520ilb; Wed, 25 Nov 2020 23:24:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJxhl7Pl4lsWO8IuOTmNRPmE0XahCFWrK3TDX/T4/Sl6E2iY6KCrycBShW7skUeOr1Mjrbeu X-Received: by 2002:a50:a45c:: with SMTP id v28mr1256867edb.329.1606375484462; Wed, 25 Nov 2020 23:24:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606375484; cv=none; d=google.com; s=arc-20160816; b=icbe5q0PESUx30vEFx0vo6TxvK8ubzzEuuSAHAN+Bp4JCDeXJxf8iKLm/Qn3b1vUn9 JvpIKtNgfMUnSRg1SdAM2Lq4BuQem2CmbK6Hn3qspo/fXG2yQgEGnNMrkl7Yx32mkn5q OnXE+zlyfAksNhOCjZti+Ve4Ui0VCJuuCARIPRTz/sdwxAJ/B8h0bvyrbujJ/6oRQuvQ U3apuji453btvBx645GWZZr8TjHdWcZeoV60YrLJJEhyMfly2bT2uGuMm1X8vrf64yBb xUCSr88m+xNZydEJfHZAl+dDBsKidHVSntLHsg+W5zTQiktdXQ4+nrWVhjoDgehm64mQ 8JcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=2Q56A6z74jHoYoTkjeOjzuUuAU4EjwzNgIpCUrXAkjI=; b=lYB02I/MEx6N9u3ckzUSCzVPfTtHWJLADmYyLU0ehlqON6mO6SC8rfE6nVk+RBa8gA iUcmqreB9ukdCwtYJMMJlJIDK2D4yHRXgKbmY9K/Ub/ba+0Ze5bkcHYeNse6g2ax0c9W 1UGX9wKuKLlI3MaRh7MBFKRG6C2ruS6MIrJR7OrCA1pe7gfOZ0xSv0qaEAfpCgbJ9nhB 1Rch8aWcDqL0HE46Y6AfUvtLsnjnmJfQcOg55B06VF+TF15LJup2Fn9rAPn2QJ36qqMq GJxEQ1oBQX7Q0L7DXCiG5APisy5tcm8z7y1rcNoehz4pmONApssbRA2I35uSmICIcloz xfqw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y11si2875812edp.494.2020.11.25.23.24.44; Wed, 25 Nov 2020 23:24:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388494AbgKZHYf (ORCPT + 15 others); Thu, 26 Nov 2020 02:24:35 -0500 Received: from mail.kernel.org ([198.145.29.99]:42048 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727760AbgKZHYf (ORCPT ); Thu, 26 Nov 2020 02:24:35 -0500 Received: from localhost.localdomain (unknown [157.49.218.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 359732068D; Thu, 26 Nov 2020 07:24:17 +0000 (UTC) From: Manivannan Sadhasivam To: sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org Cc: bjorn.andersson@linaro.org, vkoul@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v4 6/6] clk: qcom: Add GDSC support for SDX55 GCC Date: Thu, 26 Nov 2020 12:51:46 +0530 Message-Id: <20201126072146.34842-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201126072146.34842-1-manivannan.sadhasivam@linaro.org> References: <20201126072146.34842-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add GDSC support to control the power supply of power domains in SDX55 GCC. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/gcc-sdx55.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) -- 2.25.1 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 7897a3947e6d..05055fd18e6e 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -415,6 +415,7 @@ config SDM_LPASSCC_845 config SDX_GCC_55 tristate "SDX55 Global Clock Controller" + select QCOM_GDSC help Support for the global clock controller on SDX55 devices. Say Y if you want to use peripheral devices such as UART, diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c index bf114165e24b..e3b9030b2bae 100644 --- a/drivers/clk/qcom/gcc-sdx55.c +++ b/drivers/clk/qcom/gcc-sdx55.c @@ -17,6 +17,7 @@ #include "clk-pll.h" #include "clk-rcg.h" #include "clk-regmap.h" +#include "gdsc.h" #include "reset.h" enum { @@ -1455,6 +1456,30 @@ static struct clk_branch gcc_xo_pcie_link_clk = { }, }; +static struct gdsc usb30_gdsc = { + .gdscr = 0x0b004, + .pd = { + .name = "usb30_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc pcie_gdsc = { + .gdscr = 0x37004, + .pd = { + .name = "pcie_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc emac_gdsc = { + .gdscr = 0x47004, + .pd = { + .name = "emac_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_regmap *gcc_sdx55_clocks[] = { [GCC_AHB_PCIE_LINK_CLK] = &gcc_ahb_pcie_link_clk.clkr, [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, @@ -1560,6 +1585,12 @@ static const struct qcom_reset_map gcc_sdx55_resets[] = { [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0xe000 }, }; +static struct gdsc *gcc_sdx55_gdscs[] = { + [USB30_GDSC] = &usb30_gdsc, + [PCIE_GDSC] = &pcie_gdsc, + [EMAC_GDSC] = &emac_gdsc, +}; + static const struct regmap_config gcc_sdx55_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -1574,6 +1605,8 @@ static const struct qcom_cc_desc gcc_sdx55_desc = { .num_clks = ARRAY_SIZE(gcc_sdx55_clocks), .resets = gcc_sdx55_resets, .num_resets = ARRAY_SIZE(gcc_sdx55_resets), + .gdscs = gcc_sdx55_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_sdx55_gdscs), }; static const struct of_device_id gcc_sdx55_match_table[] = {