From patchwork Fri Oct 30 16:34:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 320004 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp1563409ilc; Fri, 30 Oct 2020 09:34:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxCjxfYYK49EE/ZbsOv4gh2mr1jH0/eusl1z01YJLT4plS+DAAtRemwcHii0yRLetPq7WSb X-Received: by 2002:a50:cf45:: with SMTP id d5mr3256915edk.225.1604075671563; Fri, 30 Oct 2020 09:34:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1604075671; cv=none; d=google.com; s=arc-20160816; b=skzzBNJxZ1IRGwK7gOjCL46/ZiiAcQ4g1LeQGnv/rPGUjq/G3mt+awOc+BNkGHJFvt ME85OJpRU2xvmK9OdOEReE1iyntmzueeJB2nnZoWZaYZd7k/Y135H6WYNyPK5NLci6iK iZiwctNCwoSjZ9YaBHwSMqsIpLZO8plt+xAL014XneYnbW3XG/y56be/cDGORx0ivjGz D3AJG/RzXU/t5ciy/O6uUE5GiVsEzFRjQ5wH5WuHBbp9tCCXR1EMBLPUrGpP/pAXH5SV kEJkV++gZyJoNO/kwrSnrGgDjfD8DLkUacV0SQ07fM/BbdnzAFDu/2URWbmi3sDptveX 1GcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OYYG+bPEQAKrvnUyay3Ge798oMm5TIrWSkpr0tXXXgA=; b=f9Jb4O2tPNeyNP8HdgvNrDszQoGRmlT3AF03GOJzHKjnxTjfupAc3yWGMDORy5dYB/ 1Z+4vvak2ZzfHHsl+6/Oy/ojqahqkOwk5wXQ4/6OVQo676pQbLl/Wncah2vdbBjsVTvA 7djrm3ZVA7CwdExdS/bbbIf5D3lKRwe8iSFDta58FzmrT01pzsDqfDaqcUwdxxcYTXEY nWHtSc2JwQhzAAR3b7VSPAXUw2Or9nJ9tYqXIY0bEf09X7x0EWmm1XBWibX4OlBt2Rb7 NqjZavPzTHNite7ZREKc4j8dMZC1vnir15+qHmyhlDE1rH84Zkl5gRCRRCKnG0Ki+fs9 MaGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IPXpUuBY; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id 19si4991047ejy.97.2020.10.30.09.34.31; Fri, 30 Oct 2020 09:34:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IPXpUuBY; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727205AbgJ3Qea (ORCPT + 15 others); Fri, 30 Oct 2020 12:34:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727163AbgJ3Qe3 (ORCPT ); Fri, 30 Oct 2020 12:34:29 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C2D6C0613D6 for ; Fri, 30 Oct 2020 09:34:29 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id i16so1736459wrv.1 for ; Fri, 30 Oct 2020 09:34:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OYYG+bPEQAKrvnUyay3Ge798oMm5TIrWSkpr0tXXXgA=; b=IPXpUuBYHk3ry3LWCiDQtSu6JVXDRMasFEoSmK0oT5trABpOaXDfsD728+f337p+lI ny80+nakxBsl5E5OT0ehurxFoDzVSQmTijOASIgnXyAFbkfnyjoqHNJ1F5GDZEX7vb8f wLQAWg2f6JKwz+Y7vmg31ax+0UmLS4JcwQnLIGdAdLl5GAHwQYQJ8ySrmIZCG0dsggXP hWEwyvfMF9RbsDxxfkKw8qEGhCVKLKg5MXWryea2MXp9Di31OysTGNr+SzvXFqvy32ii BCxUvQCtzMDB0Meg2q6/YicGfLCQtwWyIQaLyO9GP8AvmpOjqFXDXCvBNl7SveASSvwP 5ysA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OYYG+bPEQAKrvnUyay3Ge798oMm5TIrWSkpr0tXXXgA=; b=SNryErVusEU1UecH1nThgoFgIfpUNJJHzntWLd+AY9IiG3cq8hu6PqywvmjxZZlHmh yu/KfT9VLrr91TYp7jh/ge1aSQt73CPPIwg3mc2+GKMZ8zpcsVNblmXUz5v3LGu6AJiE arav4TMoACYG490Nb3k9SzzMIoihuaz7e9zZu73XKKW0cKVDtr+n3ldQIGDmSVyWyHrD NoaXF5N3UEKp16OLCo9VNN7zApsedadn+YnKy810mpqQQMVllvBlXYRaFfTCRpgsdn5r IlK13ldS0BG0+gPU51ZeupVWdxChMnbLB2feHfJbiAa00etP3/Ye8diH0fDxxjKCUahT Ekpg== X-Gm-Message-State: AOAM5329YJTJnOGPgpatCRBfkNm0nFd5Knd0t5DEgbElh6ArzpLsWVBe iwh4ZpLwCSs4BoLcD87/K2CANA== X-Received: by 2002:adf:ef45:: with SMTP id c5mr4507644wrp.117.1604075668061; Fri, 30 Oct 2020 09:34:28 -0700 (PDT) Received: from srini-hackbox.lan (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.gmail.com with ESMTPSA id z6sm5031989wmi.1.2020.10.30.09.34.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Oct 2020 09:34:27 -0700 (PDT) From: Srinivas Kandagatla To: linus.walleij@linaro.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 1/2] dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings Date: Fri, 30 Oct 2020 16:34:20 +0000 Message-Id: <20201030163421.14041-2-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20201030163421.14041-1-srinivas.kandagatla@linaro.org> References: <20201030163421.14041-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree binding Documentation details for Qualcomm SM8250 LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver. Signed-off-by: Srinivas Kandagatla --- .../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 129 ++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml -- 2.21.0 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..8a0732574aee --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) + Low Power Island (LPI) TLMM block + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + LPASS LPI IP on most Qualcomm SoCs + +properties: + compatible: + const: qcom,sm8250-lpass-lpi-pinctrl + + reg: + minItems: 2 + maxItems: 2 + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '^.*$': + if: + type: object + then: + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9])$" + minItems: 1 + maxItems: 14 + + function: + enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data1, qua_mi2s_ws, + swr_tx_data2, qua_mi2s_data0, swr_rx_clk, qua_mi2s_data1, + swr_rx_data1, qua_mi2s_data2, swr_tx_data3, swr_rx_data2, + dmic1_clk, i2s1_clk, dmic1_data, i2s1_ws, dmic2_clk, + i2s1_data0, dmic2_data, i2s1_data1, i2s2_clk, wsa_swr_clk, + i2s2_ws, wsa_swr_data, dmic3_clk, i2s2_data0, dmic3_data, + i2s2_data1 ] + description: + Specify the alternative function to be configured for the specified + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + lpi_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm8250-lpass-lpi-pinctrl"; + reg = <0x33c0000 0x20000>, + <0x355a000 0x1000>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 14>; + };