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[23.128.96.18]) by mx.google.com with ESMTP id x23si4428163ejc.63.2020.09.10.14.27.01; Thu, 10 Sep 2020 14:27:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xGTfHy55; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728089AbgIJV04 (ORCPT + 15 others); Thu, 10 Sep 2020 17:26:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731110AbgIJOK1 (ORCPT ); Thu, 10 Sep 2020 10:10:27 -0400 Received: from mail-lf1-x144.google.com (mail-lf1-x144.google.com [IPv6:2a00:1450:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 509D7C0617AB for ; Thu, 10 Sep 2020 07:00:15 -0700 (PDT) Received: by mail-lf1-x144.google.com with SMTP id z19so3654530lfr.4 for ; Thu, 10 Sep 2020 07:00:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0I6pQWwOhUWc2K65OlZG19X3KN2sWbUfhTEkKlMLufk=; b=xGTfHy55igiiYK6bgyw405lH2EtFNFnJvlAcrXT54GNglJh7Bis2x8BKPsrJjQBFWD BFKd6CogmmwW5E/AMPL6G/vQNXNKyMv8MI+RqUlYvL/WYvnetd119tZCxTSqsXzxvBdA khyOlWSRZgdmBaWgGwEqrfsbJqygyju+9Q9X7lNGRvlbE3Icjn1j/iGUcp3tmGtrtPHs bzXsuHxFeHULvWaSR0d2Tnns0O2KYkw/ss/FiHR/xpdSNU/qBgvGMxo76dnIhk7B5Twl ohVt6KfNJNOdBxJ2KUEEcYWNjn5C0guN4QsqMzZ245bEvihqCZATAnf7/EWh6MDuXjzp PgXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0I6pQWwOhUWc2K65OlZG19X3KN2sWbUfhTEkKlMLufk=; b=a/G5+pi/tSebClhuod/kyMgdVYITRNheVRj694Htdcx4tRaKHf2kjVJ5cgf5yDEeFV 7rldKQ6pxOJgS2lvtIfcooufWrGoNPnKjB9PDaNcUmtkNS0PWCQUjDO/ApXjqLr1R1Fb 0HoAoAR6laoH/YHaetXpoKUY9KZA0IqTeAGtojtycThxsEpOBM0TucCaVU6IsSYYFVS9 fGZ1GcvEFWbOyPrVhV11u7yz1t4IRRw0wLZ7kft2rDU7l0/fUyqDVJ+UaVKs0f7/OS43 xH+HeHbxJj7gfzwmnFj4oTf87ni9byxaEW6KHDIDVChG5U2q3vkwRo10L0hy2Zv+Xb1d oiUA== X-Gm-Message-State: AOAM533HkL0cWnEkSHipt0lv0vQ2Wrxs0jbSTi8uTwmPRVg5mgluDkz1 0oyf8sU1Yg73z5+m9t7/6e/2hw== X-Received: by 2002:a19:dc19:: with SMTP id t25mr4235141lfg.114.1599746413666; Thu, 10 Sep 2020 07:00:13 -0700 (PDT) Received: from eriador.lan ([188.162.64.156]) by smtp.gmail.com with ESMTPSA id t82sm1367646lff.43.2020.09.10.07.00.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 07:00:13 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v4 02/10] dt-bindings: thermal: qcom: add adc-thermal monitor bindings Date: Thu, 10 Sep 2020 16:59:52 +0300 Message-Id: <20200910140000.324091-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200910140000.324091-1-dmitry.baryshkov@linaro.org> References: <20200910140000.324091-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add bindings for thermal monitor, part of Qualcomm PMIC5 chips. It is a close counterpart of VADC part of those PMICs. Signed-off-by: Dmitry Baryshkov --- .../bindings/thermal/qcom-spmi-adc-tm5.yaml | 151 ++++++++++++++++++ 1 file changed, 151 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml -- 2.28.0 Reviewed-by: Jonathan Cameron diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml new file mode 100644 index 000000000000..432a65839b89 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom-spmi-adc-tm5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC ADC Thermal Monitoring +maintainers: + - Dmitry Baryshkov + +properties: + compatible: + const: qcom,spmi-adc-tm5 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + description: + Number of cells required to uniquely identify the thermal sensors. Since + we have multiple sensors this is set to 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + qcom,avg-samples: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of samples to be used for measurement. + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + default: 1 + + qcom,decimation: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This parameter is used to decrease ADC sampling rate. + Quicker measurements can be made by reducing decimation ratio. + enum: + - 250 + - 420 + - 840 + default: 840 + +patternProperties: + "^([-a-z0-9]*)@[0-9]+$": + type: object + description: + Represent one thermal sensor. + + properties: + reg: + description: Specify the sensor channel. + maxItems: 1 + + io-channels: + description: + From common IIO binding. Used to pipe PMIC ADC channel to thermal monitor + + qcom,adc-channel: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Corresponding ADC channel ID. + + qcom,ratiometric: + $ref: /schemas/types.yaml#/definitions/flag + description: + Channel calibration type. + If this property is specified VADC will use the VDD reference + (1.875V) and GND for channel calibration. If property is not found, + channel will be calibrated with 0V and 1.25V reference channels, + also known as absolute calibration. + + qcom,hw-settle-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Time between AMUX getting configured and the ADC starting conversion. + + qcom,pre-scaling: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Used for scaling the channel input signal before the + signal is fed to VADC. See qcom,spi-vadc specification for the list + of possible values. + minItems: 2 + maxItems: 2 + + required: + - reg + - qcom,adc-channel + + additionalProperties: + false + +required: + - compatible + - reg + - interrupts + - "#address-cells" + - "#size-cells" + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include + #include + spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + pm8150b_adc: adc@3100 { + reg = <0x3100>; + compatible = "qcom,spmi-adc5"; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Other propreties are omitted */ + conn-therm@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + + pm8150b_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + conn-therm@0 { + reg = <0>; + io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,adc-channel = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + }; +...