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[23.128.96.18]) by mx.google.com with ESMTP id g19si12790ejf.115.2020.08.20.20.55.58; Thu, 20 Aug 2020 20:55:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727084AbgHUDz6 (ORCPT + 15 others); Thu, 20 Aug 2020 23:55:58 -0400 Received: from mail-io1-f67.google.com ([209.85.166.67]:34045 "EHLO mail-io1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727845AbgHUDz4 (ORCPT ); Thu, 20 Aug 2020 23:55:56 -0400 Received: by mail-io1-f67.google.com with SMTP id q75so487770iod.1; Thu, 20 Aug 2020 20:55:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1SzKekjf6fRGgLEC8a7Q0N4huYSGdxsop7/CqILDTfo=; b=n6B3EDPxP0YV6Mcp6xnpT4zsSsGeeXxUm68RA5OO6uBmalyRrgEZennjl28Fg9k6UE YWAv3eXzVxREgEk4+7hLuPsoFmdLN7H1tir2F3PK/23y5Ht6Nuk9QNx7tshzeTiqDxye J1VqPtOVFYL3IolYXqGaFWbdNTz9OXdpvKNpUrkCL8vTW46GN7KT5mA7Af4yeTQDhFrs 98Nye+dL1Kvx6afSc+xL6J62KESPHRrnnZ/LhTcByHb2DOLYhwH6zrDqf9Mm01jRJSaK lueXR2pCjY4RxWGwYJXpw5D7A+zhJUWyXv2w9bba/mMlwbZeboswx8+rljUYElbytKnQ dQhw== X-Gm-Message-State: AOAM531Kgmkyj+R1VQwfIoBYYMm8UAkNQ5q2yrtsq2/TFSs58m+IoQAm eAJzJd+6boeI+srU/C/Q5Q== X-Received: by 2002:a05:6638:25d3:: with SMTP id u19mr821718jat.103.1597982155028; Thu, 20 Aug 2020 20:55:55 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.249]) by smtp.googlemail.com with ESMTPSA id 79sm413923ilc.9.2020.08.20.20.55.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2020 20:55:54 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Lorenzo Pieralisi Cc: linux-pci@vger.kernel.org, Andy Gross , Binghui Wang , Bjorn Andersson , Dilip Kota , Fabio Estevam , Gustavo Pimentel , Jerome Brunet , Jesper Nilsson , Jingoo Han , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , Lucas Stach , Martin Blumenstingl , Masahiro Yamada , Murali Karicheri , Neil Armstrong , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang , Marc Zyngier , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 22/40] PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL Date: Thu, 20 Aug 2020 21:54:02 -0600 Message-Id: <20200821035420.380495-23-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200821035420.380495-1-robh@kernel.org> References: <20200821035420.380495-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PCIE_LINK_WIDTH_SPEED_CONTROL is already defined in pcie-designware.h, so remove it from the i.MX6 driver. Cc: Richard Zhu Cc: Lucas Stach Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-imx6.c | 2 -- 1 file changed, 2 deletions(-) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 68a09680e728..2b075a468104 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -116,8 +116,6 @@ struct imx6_pcie { #define PCIE_PHY_STAT (PL_OFFSET + 0x110) #define PCIE_PHY_STAT_ACK BIT(16) -#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C - /* PHY registers (not memory-mapped) */ #define PCIE_PHY_ATEOVRD 0x10 #define PCIE_PHY_ATEOVRD_EN BIT(2)