From patchwork Mon Aug 3 21:00:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 250789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDE9BC433ED for ; Mon, 3 Aug 2020 21:01:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D298422BED for ; Mon, 3 Aug 2020 21:01:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1596488490; bh=8Irn/YdkHb2QXNwssXPmCIL8uhGjYFUfAiI3OQQsIhI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=e2g6Q1yx3uFGSIX30SRPq/hfJ2e8iBhJHLpQxqBwC60KT+9I8BeLBZ+bkXmkDj3dZ zAfaZj5zNOQxBglCy61vfOeXB/ytLkRNQSRpWQr/Xv6TePA/UbpFy3JkAUca+dnpk0 2T20am4uJQX4p+WawI9XAbWWF5sYm0RhNKxtKwxE= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729345AbgHCVB3 (ORCPT ); Mon, 3 Aug 2020 17:01:29 -0400 Received: from mail-io1-f66.google.com ([209.85.166.66]:38423 "EHLO mail-io1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729344AbgHCVB1 (ORCPT ); Mon, 3 Aug 2020 17:01:27 -0400 Received: by mail-io1-f66.google.com with SMTP id l1so39991437ioh.5; Mon, 03 Aug 2020 14:01:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ijQ8ATU40Ukxf+vdFPpN/cTBNWQIy8LHFEwNkXuS7vE=; b=TtA3D50HOWjGSOYcI0fLq7MAUnDBSi++nGASm4Aoh/xGbxG+Nth6WBRpCcWzR9SZpJ zXFkOFhdk5CglhnIbRVhmHVnrTacwOWTsbwSRutc8x0VmJKmquUL+Gsix5cdpmcsFwQz k0+kaJQSrIPorGnuaRYv9orYBj9W0AYPkcJe7trNLYw/agEG2PAuWh4BjPBgOjPjVSg8 Pwsc5AphA4aWpxRoxYG36XEP47a81vesf02tunJ5SNy+qKfpGxOeW++4gDyBA4TwHmyB Eq121ULzAvJ6cWj5psaqF7VRaLKEH/0fSCEaHlmY4VaVJYSKZO/gmO4qxftZGmUIOTff TY3w== X-Gm-Message-State: AOAM532GpYjM3KbWCmeSb05lEiLzZCNVZwWkvEuYlBu6FitDnYc5T/Gp YmOiADsJm8DwexS5xjTDBQ== X-Google-Smtp-Source: ABdhPJwDDB+OwHWjJuTy7sDEknkVzY4VCrs5f0YZ1QmljRmggfDq+USGhZLjxDletIoYITtztOCGKA== X-Received: by 2002:a05:6638:2482:: with SMTP id x2mr1801792jat.55.1596488486266; Mon, 03 Aug 2020 14:01:26 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:25 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 03/27] PCI: dwc: Allow overriding bridge pci_ops Date: Mon, 3 Aug 2020 15:00:52 -0600 Message-Id: <20200803210116.3132633-4-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In preparation to allow drivers to set their own root and child pci_ops instead of using the DWC specific config space ops, we need to make the pci_host_bridge pointer available and move setting the bridge->ops and bridge->child_ops pointer to before the .host_init() hook. Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-designware-host.c | 15 ++++++++++----- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 6232aefbbdb4..7cd8c9528d4c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -344,6 +344,8 @@ int dw_pcie_host_init(struct pcie_port *pp) if (!bridge) return -ENOMEM; + pp->bridge = bridge; + ret = pci_parse_request_of_pci_ranges(dev, &bridge->windows, &bridge->dma_ranges, NULL); if (ret) @@ -450,6 +452,10 @@ int dw_pcie_host_init(struct pcie_port *pp) } } + /* Set default bus ops */ + bridge->ops = &dw_pcie_ops; + bridge->child_ops = &dw_pcie_ops; + if (pp->ops->host_init) { ret = pp->ops->host_init(pp); if (ret) @@ -461,7 +467,6 @@ int dw_pcie_host_init(struct pcie_port *pp) bridge->dev.parent = dev; bridge->sysdata = pp; bridge->busnr = pp->root_bus_nr; - bridge->ops = &dw_pcie_ops; bridge->map_irq = of_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle; @@ -667,11 +672,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCI_COMMAND, val); /* - * If the platform provides ->rd_other_conf, it means the platform - * uses its own address translation component rather than ATU, so - * we should not program the ATU here. + * If the platform provides its own child bus config accesses, it means + * the platform uses its own address translation component rather than + * ATU, so we should not program the ATU here. */ - if (!pp->ops->rd_other_conf) { + if (pp->bridge->child_ops == &dw_pcie_ops && !pp->ops->rd_other_conf) { dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, PCIE_ATU_TYPE_MEM, pp->mem_base, pp->mem_bus_addr, pp->mem_size); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 656e00f8fbeb..bad3cddab28e 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -201,6 +201,7 @@ struct pcie_port { u32 num_vectors; u32 irq_mask[MAX_MSI_CTRLS]; struct pci_bus *root_bus; + struct pci_host_bridge *bridge; raw_spinlock_t lock; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); };