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[83.6.170.196]) by smtp.googlemail.com with ESMTPSA id lm22sm1523448ejb.109.2020.06.25.11.21.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2020 11:21:27 -0700 (PDT) From: Konrad Dybcio To: skrzynka@konradybcio.pl Cc: Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , Kees Cook , Anton Vorontsov , Colin Cross , Tony Luck , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 02/13] arm64: dts: qcom: msm8992: Fix SDHCI1 Date: Thu, 25 Jun 2020 20:21:06 +0200 Message-Id: <20200625182118.131476-3-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200625182118.131476-1-konradybcio@gmail.com> References: <20200625182118.131476-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This commit ensures the correct IRQ type is set and disables the device by default. The mmc-hs400-1_8v property is also moved to Bullhead as it might not be present on all boards. The node has been renamed to sdhci@ instead of mmc@ and the phandle was changed to sdhc_1 to comply with the newer DTS style. Signed-off-by: Konrad Dybcio --- .../boot/dts/qcom/msm8992-bullhead-rev-101.dts | 6 ++++++ arch/arm64/boot/dts/qcom/msm8992.dtsi | 16 +++++++++------- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts index a2de69292d28..1061fd5404aa 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts @@ -271,3 +271,9 @@ pm8994_l32: l32 { }; }; }; + +&sdhc_1 { + status = "okay"; + + mmc-hs400-1_8v; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 43b2e4cd26f0..8ef1cb8ba8ef 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -158,18 +158,19 @@ frame@f9028000 { }; }; - sdhci1: mmc@f9824900 { + sdhc_1: sdhci@f9824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; - interrupts = , - ; + interrupts = , + ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on @@ -179,8 +180,9 @@ sdhci1: mmc@f9824900 { regulator-always-on; bus-width = <8>; - mmc-hs400-1_8v; - status = "okay"; + non-removable; + + status = "disabled"; }; blsp1_uart2: serial@f991e000 {