From patchwork Mon Jan 13 21:31:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 190682 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD62CC33CB3 for ; Mon, 13 Jan 2020 21:32:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7DD702084D for ; Mon, 13 Jan 2020 21:32:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="loZIm2Dm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728833AbgAMVcT (ORCPT ); Mon, 13 Jan 2020 16:32:19 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:45233 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726488AbgAMVcT (ORCPT ); Mon, 13 Jan 2020 16:32:19 -0500 Received: by mail-wr1-f67.google.com with SMTP id j42so10133112wrj.12 for ; Mon, 13 Jan 2020 13:32:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YB3f30pJRu3JULH7XG/mWzUNFJ0TPVlsc2Y5J8rGS1s=; b=loZIm2DmjP7LLbkcSfhjNC5e0geDOGuSIjTRZ283isVHaWZOdF5Kl/QgfvQaQqRc2D lhkaRw6bgvApu+45+oytDfmFZsftlZcotNeLA58W3RByo/UGV/uZVJlmKQEe+tr1+EDG ggBD61U19lbXEFoCN3YmOWFmkE0UiojsNb8ifwmkwsa8NwSjSea2C2QPoSffWqmkd78G 7qcKQhH++eIOfwUHXTWmWQYayFyAQDJTZzxKsLIdUIfWLZS5G3Pch7rMP4ZjPzUWccZX 6zoRAMvcdJugz0kJrCK3IeHzckXBemXyTbBmr+aS1bZxJVAyJeyQZdMqOn2m3U8Jbm+x NTdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YB3f30pJRu3JULH7XG/mWzUNFJ0TPVlsc2Y5J8rGS1s=; b=s2hlbP7WhMFdXS6saguFoJHMcePvh0kepIydszWMt4FH8SGQfvJLinlqhEKF0B6Bxm wlQ2UOzBazeCBm1H7cA4O+Fdal/r0alygkqpwd3Ier5NRK8PEAb03KRov/eOL7iKnSJ5 XaaIFte412XlPZAZ7yFB7etIK0a3K54vQH0/xTajW2S8F3NFIMOjAJpxP0RaTBkguoV/ P4wvuktlWwqI9fldMnqD+irO2n8M82HvgVSO2YBlAk5WeuszmeGLZaWFoueT1aLe3Ga2 6isG3v0rA+pzoeYQgtVkObhjWN0uYLhYoLFQWec/Qn4jNHAXOyFt0OKLNQCEmiPsgQV2 pF9Q== X-Gm-Message-State: APjAAAU/KIflytqFFACtzkLSUzuPmfV79e6DxMqdlUW/BLlnhUYtOqlY C8bTdwViuUcyzX8e0qcvCqxcJw== X-Google-Smtp-Source: APXvYqwR33GRhP96SSBraPh6Yc0sSHjj9ZfYnFPOIiH4XK2mRAlRbt4YSasNPPteW5EHr3zq6AmP6Q== X-Received: by 2002:adf:edd0:: with SMTP id v16mr20750645wro.310.1578951136868; Mon, 13 Jan 2020 13:32:16 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:a1cf:b00b:5683:ed40]) by smtp.gmail.com with ESMTPSA id j12sm16725120wrt.55.2020.01.13.13.32.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2020 13:32:14 -0800 (PST) From: Mike Leach To: mike.leach@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, coresight@lists.linaro.org, linux-doc@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, mathieu.poirier@linaro.org, suzuki.poulose@arm.com, robh+dt@kernel.org, maxime@cerno.tech, liviu.dudau@arm.com, sudeep.holla@arm.com, lorenzo.pieralisi@arm.com, agross@kernel.org, corbet@lwn.net Subject: [PATCH v8 10/15] dt-bindings: qcom: Add CTI options for qcom msm8916 Date: Mon, 13 Jan 2020 21:31:44 +0000 Message-Id: <20200113213149.25599-11-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200113213149.25599-1-mike.leach@linaro.org> References: <20200113213149.25599-1-mike.leach@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adds system and CPU bound CTI definitions for Qualcom msm8916 platform (Dragonboard DB410C). System CTIs 2-11 are omitted as no information available at present. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier Acked-by: Suzuki K Poulose --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 85 +++++++++++++++++++++++++-- 1 file changed, 81 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 8686e101905c..68587968f5c0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -1357,7 +1358,7 @@ cpu = <&CPU3>; }; - etm@85c000 { + etm0: etm@85c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85c000 0x1000>; @@ -1375,7 +1376,7 @@ }; }; - etm@85d000 { + etm1: etm@85d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85d000 0x1000>; @@ -1393,7 +1394,7 @@ }; }; - etm@85e000 { + etm2: etm@85e000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85e000 0x1000>; @@ -1411,7 +1412,7 @@ }; }; - etm@85f000 { + etm3: etm@85f000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85f000 0x1000>; @@ -1429,6 +1430,82 @@ }; }; + /* System CTIs */ + /* CTI 0 - TMC connections */ + cti@810000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x810000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + /* CTI 1 - TPIU connections */ + cti@811000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x811000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + /* CTIs 2-11 - no information - not instantiated */ + + /* Core CTIs; CTIs 12-15 */ + /* CTI - CPU-0 */ + cti@858000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x858000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU0>; + arm,cs-dev-assoc = <&etm0>; + + }; + + /* CTI - CPU-1 */ + cti@859000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x859000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + arm,cs-dev-assoc = <&etm1>; + }; + + /* CTI - CPU-2 */ + cti@85a000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x85a000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU2>; + arm,cs-dev-assoc = <&etm2>; + }; + + /* CTI - CPU-3 */ + cti@85b000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x85b000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + arm,cs-dev-assoc = <&etm3>; + }; + + venus: video-codec@1d00000 { compatible = "qcom,msm8916-venus"; reg = <0x01d00000 0xff000>;