| Message ID | 20190826164510.6425-1-jorge.ramirez-ortiz@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/5] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency | expand |
Quoting Jorge Ramirez (2019-09-05 00:30:42) > On 8/26/19 18:45, Jorge Ramirez-Ortiz wrote: > > Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware > > specifications. > > > > Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> > > Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> > > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> > > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > Acked-by: Stephen Boyd <sboyd@kernel.org> > > --- > > drivers/clk/qcom/clk-alpha-pll.c | 8 ++++++++ > > drivers/clk/qcom/clk-alpha-pll.h | 1 + > > drivers/clk/qcom/gcc-qcs404.c | 2 +- > > 3 files changed, 10 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > > index 055318f97991..9228b7b1f56e 100644 > > --- a/drivers/clk/qcom/clk-alpha-pll.c > > +++ b/drivers/clk/qcom/clk-alpha-pll.c > > @@ -878,6 +878,14 @@ static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate, > > return clamp(rate, min_freq, max_freq); > > } > > > > +const struct clk_ops clk_alpha_pll_fixed_ops = { > > + .enable = clk_alpha_pll_enable, > > + .disable = clk_alpha_pll_disable, > > + .is_enabled = clk_alpha_pll_is_enabled, > > + .recalc_rate = clk_alpha_pll_recalc_rate, > > +}; > > +EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); > > + > > const struct clk_ops clk_alpha_pll_ops = { > > .enable = clk_alpha_pll_enable, > > .disable = clk_alpha_pll_disable, > > diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h > > index 15f27f4b06df..c28eb1a08c0c 100644 > > --- a/drivers/clk/qcom/clk-alpha-pll.h > > +++ b/drivers/clk/qcom/clk-alpha-pll.h > > @@ -109,6 +109,7 @@ struct alpha_pll_config { > > }; > > > > extern const struct clk_ops clk_alpha_pll_ops; > > +extern const struct clk_ops clk_alpha_pll_fixed_ops; > > extern const struct clk_ops clk_alpha_pll_hwfsm_ops; > > extern const struct clk_ops clk_alpha_pll_postdiv_ops; > > extern const struct clk_ops clk_alpha_pll_huayra_ops; > > diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c > > index e12c04c09a6a..567140709c7d 100644 > > --- a/drivers/clk/qcom/gcc-qcs404.c > > +++ b/drivers/clk/qcom/gcc-qcs404.c > > @@ -330,7 +330,7 @@ static struct clk_alpha_pll gpll0_ao_out_main = { > > .parent_names = (const char *[]){ "cxo" }, > > .num_parents = 1, > > .flags = CLK_IS_CRITICAL, > > - .ops = &clk_alpha_pll_ops, > > + .ops = &clk_alpha_pll_fixed_ops, > > }, > > }, > > }; > > > > just a quick follow up, is this series being picked-up? No cover letter! ;P Anyway, I'll pick it up.
Quoting Jorge Ramirez-Ortiz (2019-08-26 09:45:10) > When COMMON_CLK_DISABLED_UNUSED is set, in an effort to save power and > to keep the software model of the clock in line with reality, the > framework transverses the clock tree and disables those clocks that > were enabled by the firmware but have not been enabled by any device > driver. > > If CPUFREQ is enabled, early during the system boot, it might attempt > to change the CPU frequency ("set_rate"). If the HFPLL is selected as > a provider, it will then change the rate for this clock. > > As boot continues, clk_disable_unused_subtree will run. Since it wont > find a valid counter (enable_count) for a clock that is actually > enabled it will attempt to disable it which will cause the CPU to > stop. Notice that in this driver, calls to check whether the clock is > enabled are routed via the is_enabled callback which queries the > hardware. > > The following commit, rather than marking the clock critical and > forcing the clock to be always enabled, addresses the above scenario > making sure the clock is not disabled but it continues to rely on the > firmware to enable the clock. > > Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> > Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- Also this one. Seems fine to merge immediately vs the ones that do some DT trickery.
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 055318f97991..9228b7b1f56e 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -878,6 +878,14 @@ static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate, return clamp(rate, min_freq, max_freq); } +const struct clk_ops clk_alpha_pll_fixed_ops = { + .enable = clk_alpha_pll_enable, + .disable = clk_alpha_pll_disable, + .is_enabled = clk_alpha_pll_is_enabled, + .recalc_rate = clk_alpha_pll_recalc_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); + const struct clk_ops clk_alpha_pll_ops = { .enable = clk_alpha_pll_enable, .disable = clk_alpha_pll_disable, diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 15f27f4b06df..c28eb1a08c0c 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -109,6 +109,7 @@ struct alpha_pll_config { }; extern const struct clk_ops clk_alpha_pll_ops; +extern const struct clk_ops clk_alpha_pll_fixed_ops; extern const struct clk_ops clk_alpha_pll_hwfsm_ops; extern const struct clk_ops clk_alpha_pll_postdiv_ops; extern const struct clk_ops clk_alpha_pll_huayra_ops; diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index e12c04c09a6a..567140709c7d 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -330,7 +330,7 @@ static struct clk_alpha_pll gpll0_ao_out_main = { .parent_names = (const char *[]){ "cxo" }, .num_parents = 1, .flags = CLK_IS_CRITICAL, - .ops = &clk_alpha_pll_ops, + .ops = &clk_alpha_pll_fixed_ops, }, }, };