From patchwork Thu Jul 25 10:41:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 169699 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp11465065ilk; Thu, 25 Jul 2019 03:42:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqzHkx+eMksIM/bVhmvLq5fz+QnWr7pIqxrovUvjdCy92Q5X0JiAyggYuOqU+uK7Rc/dfpbd X-Received: by 2002:a17:902:8509:: with SMTP id bj9mr91213827plb.79.1564051360020; Thu, 25 Jul 2019 03:42:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564051360; cv=none; d=google.com; s=arc-20160816; b=r9t0grJUUlyYxbr0BD7H4RCp8cPEKgBAMA7zqLycbqznNeKCCyjLg0ZkvEquuepOdJ qowe1td9sT0yC10Cfsjtd1I1ntJe3F7EIeaHbsYMNpMVtkUfVSUXSil2+MCoMsHpQhRH xGdFLnqsA6VGZBNPZTBqx/gRzzO07x/UfIedbHJMcWcRvEM7KcUuI6a2X3ni6LrnBtDx KOpmtDGNbIg8YW0wc+FIMuZoCUJAY5Mf/0Mgm+VaT9PhiWF35DyYgvn/8RG58IhKCJEE kPkhXmML7YQyOBpjdsSruX/COeG1r4rUZ3no5Ql7ug66tnDhfueVdSXEB/MfN6u4I7ao U3OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lthHRg+gKXUu96aNRs4HmAIZHQgiKH+Tn5IF/VHfwN4=; b=uM5CWZS+wGO1Las5x0l3o4ZwQoFtgxaexSdWfiYFFaaWfSBvO5GG9HE/LsJzrugOF0 NdujlZPTb2IexEYyla1oX23ERHdtrqYiC2x850oSNE68AsjpRqsusLSlbrvs7aPtBxOF Q1+8rkoR6ud91pCnoO+gQkGFo0xadjLk4f1NJeucFl7lZhhb75L51tvpY4MomYwBZhJI vQKU7ZWHgXRNtd0ztSeJSMU76gmjRdZeE94v+mHh10u9PWlM2ZgkBC8GVKGd2kGHDFz3 a3n+TjCIzhLMK/T5azGO1iBH4mR4AGyIN/hvqfxb9z9m/V6O7UoxVcyaD6fiyrElRk37 TNSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="bik7/fTB"; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a26si22439661pgb.276.2019.07.25.03.42.39; Thu, 25 Jul 2019 03:42:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="bik7/fTB"; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387763AbfGYKmi (ORCPT + 15 others); Thu, 25 Jul 2019 06:42:38 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:46266 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389518AbfGYKmf (ORCPT ); Thu, 25 Jul 2019 06:42:35 -0400 Received: by mail-lj1-f194.google.com with SMTP id v24so47607935ljg.13 for ; Thu, 25 Jul 2019 03:42:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lthHRg+gKXUu96aNRs4HmAIZHQgiKH+Tn5IF/VHfwN4=; b=bik7/fTBpoIKUMQpRer7EZRyL8s2d/DAzqt781ZRaZF2vwO1YCG6Qs4D75TXyU/Aqd QSZ3GJWLYKpwW5o0LrZKZsEk4CJcXsv6AgCV/J7cDqOiEvjFRBIVkvtiiqQA/VjRn2qf bdC1jNuEb0T0HuwbJNSe3YVhop2MaqYHeEBujobY8fvxBU232FETSigsM6mBhv2yHcIy 5dnp3zdQU6XIbchzboRdwDQ+ZmMk0I9pjyVsyQdpXaUo2bv60Lv2nsuSJknU+y77FYls iUIOHoo8ck5x0h0baCJf43xQI3/6KainyUBCQY6+M2uIw9xKwncn8JP7KiONLBG/tzQL s5uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lthHRg+gKXUu96aNRs4HmAIZHQgiKH+Tn5IF/VHfwN4=; b=g5tRRYJ9ET6LZ4jvectVdPVmpLDvZoZQ2jGEwTQaXW6vzfyA4gdI6M2MgcO0EnJdSC 96eCTFovvbzuApnaD4Gy+M+gR04NjdFhTNpJuO6vv0IoFyg1XaaBp5potp4o2N481HgA pLZK13/TS7KlXtrpG/XC1nxnH4k+ZOIBfKgt/1w0VqnRvo2QwaNgW6hLX5rILWdDhzaz ZjfDIHkFQXvRCPznVwXxtd6VOCTLFeda5MI0U/cdFEBsd/k5WtD5FXbDYBOYNQ1GHdHG /Z9gErkOduHpIydZjlo2Yn1YMKEedNZI56xda0D/FwfqZGK58P35n44BUD35wqf+zNcQ 4ZPw== X-Gm-Message-State: APjAAAWFBrupiIUJd/mhNYSv026GTYBLuAxJeb8vomeCxAMUNMpRX8Tv z4je+OF+Ys637QMmPSRVrELp9Q== X-Received: by 2002:a2e:89ca:: with SMTP id c10mr30275573ljk.106.1564051352562; Thu, 25 Jul 2019 03:42:32 -0700 (PDT) Received: from localhost.localdomain (ua-83-226-44-230.bbcust.telenor.se. [83.226.44.230]) by smtp.gmail.com with ESMTPSA id k124sm7461299lfd.60.2019.07.25.03.42.31 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 25 Jul 2019 03:42:32 -0700 (PDT) From: Niklas Cassel To: Andy Gross , Ilia Lin , "Rafael J. Wysocki" , Viresh Kumar Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, sboyd@kernel.org, vireshk@kernel.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Niklas Cassel , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 07/14] cpufreq: qcom: Add support for qcs404 on nvmem driver Date: Thu, 25 Jul 2019 12:41:35 +0200 Message-Id: <20190725104144.22924-8-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190725104144.22924-1-niklas.cassel@linaro.org> References: <20190725104144.22924-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for qcs404 on nvmem driver. The qcs404 SoC has support for Core Power Reduction (CPR), which is implemented as a power domain provider, therefore add optional support in this driver to attach to a genpd power domain. Co-developed-by: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Niklas Cassel --- Changes since V1: -Adapt to dev_pm_opp_attach_genpd() API change. drivers/cpufreq/qcom-cpufreq-nvmem.c | 50 ++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 3 deletions(-) -- 2.21.0 diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 2d798a1685c5..f0d2d5035413 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -49,10 +50,12 @@ struct qcom_cpufreq_match_data { int (*get_version)(struct device *cpu_dev, struct nvmem_cell *speedbin_nvmem, struct qcom_cpufreq_drv *drv); + const char **genpd_names; }; struct qcom_cpufreq_drv { struct opp_table **opp_tables; + struct opp_table **genpd_opp_tables; u32 versions; const struct qcom_cpufreq_match_data *data; }; @@ -126,6 +129,12 @@ static const struct qcom_cpufreq_match_data match_data_kryo = { .get_version = qcom_cpufreq_kryo_name_version, }; +static const char *qcs404_genpd_names[] = { "cpr", NULL }; + +static const struct qcom_cpufreq_match_data match_data_qcs404 = { + .genpd_names = qcs404_genpd_names, +}; + static int qcom_cpufreq_probe(struct platform_device *pdev) { struct qcom_cpufreq_drv *drv; @@ -188,11 +197,19 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) goto free_drv; } + drv->genpd_opp_tables = kcalloc(num_possible_cpus(), + sizeof(*drv->genpd_opp_tables), + GFP_KERNEL); + if (!drv->genpd_opp_tables) { + ret = -ENOMEM; + goto free_opp; + } + for_each_possible_cpu(cpu) { cpu_dev = get_cpu_device(cpu); if (NULL == cpu_dev) { ret = -ENODEV; - goto free_opp; + goto free_genpd_opp; } if (drv->data->get_version) { @@ -203,7 +220,22 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) ret = PTR_ERR(drv->opp_tables[cpu]); dev_err(cpu_dev, "Failed to set supported hardware\n"); - goto free_opp; + goto free_genpd_opp; + } + } + + if (drv->data->genpd_names) { + drv->genpd_opp_tables[cpu] = + dev_pm_opp_attach_genpd(cpu_dev, + drv->data->genpd_names, + NULL); + if (IS_ERR(drv->genpd_opp_tables[cpu])) { + ret = PTR_ERR(drv->genpd_opp_tables[cpu]); + if (ret != -EPROBE_DEFER) + dev_err(cpu_dev, + "Could not attach to pm_domain: %d\n", + ret); + goto free_genpd_opp; } } } @@ -218,6 +250,13 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) ret = PTR_ERR(cpufreq_dt_pdev); dev_err(cpu_dev, "Failed to register platform device\n"); +free_genpd_opp: + for_each_possible_cpu(cpu) { + if (IS_ERR_OR_NULL(drv->genpd_opp_tables[cpu])) + break; + dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]); + } + kfree(drv->genpd_opp_tables); free_opp: for_each_possible_cpu(cpu) { if (IS_ERR_OR_NULL(drv->opp_tables[cpu])) @@ -238,11 +277,15 @@ static int qcom_cpufreq_remove(struct platform_device *pdev) platform_device_unregister(cpufreq_dt_pdev); - for_each_possible_cpu(cpu) + for_each_possible_cpu(cpu) { if (drv->opp_tables[cpu]) dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]); + if (drv->genpd_opp_tables[cpu]) + dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]); + } kfree(drv->opp_tables); + kfree(drv->genpd_opp_tables); kfree(drv); return 0; @@ -259,6 +302,7 @@ static struct platform_driver qcom_cpufreq_driver = { static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { { .compatible = "qcom,apq8096", .data = &match_data_kryo }, { .compatible = "qcom,msm8996", .data = &match_data_kryo }, + { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, {}, };