From patchwork Tue Feb 19 06:04:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 158670 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3296843jaa; Mon, 18 Feb 2019 22:04:08 -0800 (PST) X-Google-Smtp-Source: AHgI3IYaw2D2SE67YbC69QuaYdXL0KpCjZRwYoN4D+27yvvtowfHttIoVKnIMXe0W54Kgk2aRLA9 X-Received: by 2002:a17:902:1e8:: with SMTP id b95mr28927057plb.325.1550556248812; Mon, 18 Feb 2019 22:04:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550556248; cv=none; d=google.com; s=arc-20160816; b=voFH2HxEmXnJedjRFgg3o9+EK/e8J8xj0aCeDtT72ANEot5Fnmym9CkAXj9L+3+xfX vo+0zWhTf3C3Ce7rfCG5JlvmbWFI/dZ4XcwtlXAmfmHrP0BxWIONkDIEKQnuvvlhTJQ2 /IxZKP6BVb1VhNS3quiIhYA4otLsdv4tpfHBMbO30AKyyOUHSCOLs1725xy51aTr2a0R OZyifZaaFBdjFvFBJrhesoaJsrqyygq/BDK9bcr5ixeS/VvKbFubC1ZH3M8PybDPjTf1 NwNIBi71MUpKbbYMkDuB7bdSgsI+ZrM+vIswJLMPAKV8i4t6hbyyTJVm5E1DxRFC//Q0 6r3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=1E49ftReb7K8rzBeYHf8biDKYQclTixiO6Ek5uC1CsQ=; b=DjsrGCSpptgnzRKYmkPfHDA3dr7cY5aCgMPrWbNcGLeYb/Owpq2DcDs8Y1FiFcWH1i ZHqHC1LL0Qddo3dIc/SEshYqaDsFniRcSh6e3rpN0/JhGovOmPHq9DRH13toIqPLLwt9 /eLY8jD0RHs8BBtBMng8aR8V2Y1a+pZvAyhNf/menOpt/0K3UNC8WGTHPBZFrWAGjL84 CWGLw4AGe/OAWCdvOfkWiegsiHNsUD/5KJVSFArpKXa06bYN/hr8CVNDh6Xw/rOeD98k VVUniBVY1PFki0Lpw/vg/mRiABKj1oyg28mtrSi3QTZ+LifvN10+f4cWn9WD/fF09oc3 MLyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T6RjGrAv; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h33si14717110pgl.157.2019.02.18.22.04.08; Mon, 18 Feb 2019 22:04:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T6RjGrAv; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726902AbfBSGEF (ORCPT + 15 others); Tue, 19 Feb 2019 01:04:05 -0500 Received: from mail-pl1-f194.google.com ([209.85.214.194]:37752 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726844AbfBSGEC (ORCPT ); Tue, 19 Feb 2019 01:04:02 -0500 Received: by mail-pl1-f194.google.com with SMTP id q3so2495352pll.4 for ; Mon, 18 Feb 2019 22:04:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1E49ftReb7K8rzBeYHf8biDKYQclTixiO6Ek5uC1CsQ=; b=T6RjGrAvsunviRXAet9y3UvlQjv3YJPiNxzmSQkWH0veCqNHY6Gk4ktIfXberaskZ1 iiAlYD8JUMvQJw6kt4zL2DHEcW4GyAfMGOAH8UkByIiGzOo/50CIzz6TWlBp36+BbuCv QLIK369EvW4onecF+frafZK0XHSTVv8X34/1azG1h4PrHLmUgHY0a+AI5rURUnpVNC9A yivWLfJ6IWZcK1BbtJuzuZIqVZ7kzsHosrr1yyaqCutpRZfAN3XRnEaqWGSHN2UeUEHe 4dLtl6+1rGsaADijvz59LOZvb1Vx+KrrH9L4QdD7i8c2P/Wm8VkhUJNd6/oPYKj25VAM DcSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1E49ftReb7K8rzBeYHf8biDKYQclTixiO6Ek5uC1CsQ=; b=h2snzqb4jwzg/3Xrn1q3AjioAGKpBl9S6M6hSr5wS+2h5/5tX/6GJsX4MKDfyPzsYk nn0Oulz+dfahN9ig4NUfd7XsLY6msWxLVqrLfTLt1eSfbv6jc4DsqKWDWMnd2M5qrpRb CVnwsbqmOYXxVb1nw7YLQN9DC6VLTXuYYyUD436ptGb4olq0Ncm4lSjc0wNDUrTpCXEP ZLBsQxGXhySG0J1z/uJyc6IkQwQA470EBHSFRuLS1WPq03oiHVyITRyGD+GzFVTgYETK 4hWgUnHBLMj//Yrvar62EuYOePffvA1xVN5CTD6ND2i2Lnjk+8T/SkTH5SIzGrEzYzVq Sruw== X-Gm-Message-State: AHQUAubXQaxCNuOMS5IvpdK7VHfgM7/mVAsXFCQpjqwa4iL+CeKBlbqp 7MXfRCHx2QA/rAZoLIgS4ZuMbg== X-Received: by 2002:a17:902:584:: with SMTP id f4mr30018103plf.28.1550556241091; Mon, 18 Feb 2019 22:04:01 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id 86sm31914838pfk.157.2019.02.18.22.03.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 Feb 2019 22:04:00 -0800 (PST) From: Bjorn Andersson To: Andy Gross Cc: David Brown , Bjorn Helgaas , Rob Herring , Mark Rutland , Kishon Vijay Abraham I , Michael Turquette , Stephen Boyd , Stanimir Varbanov , Lorenzo Pieralisi , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 7/7] arm64: dts: qcom: qcs404: Add PCIe related nodes Date: Mon, 18 Feb 2019 22:04:07 -0800 Message-Id: <20190219060407.15263-8-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190219060407.15263-1-bjorn.andersson@linaro.org> References: <20190219060407.15263-1-bjorn.andersson@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, add these to the platform dtsi and enable them for the EVB with the perst gpio and analog supplies defined. Reviewed-by: Niklas Cassel Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 25 +++++++++ arch/arm64/boot/dts/qcom/qcs404.dtsi | 67 ++++++++++++++++++++++++ 2 files changed, 92 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 50b3589c7f15..579ddaf4f5fa 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -21,6 +21,22 @@ }; }; +&pcie { + status = "ok"; + + perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&perst_state>; +}; + +&pcie_phy { + status = "ok"; + + vdda-vp-supply = <&vreg_l3_1p05>; + vdda-vph-supply = <&vreg_l5_1p8>; +}; + &remoteproc_adsp { status = "ok"; }; @@ -137,6 +153,15 @@ }; &tlmm { + perst_state: perst { + pins = "gpio43"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + output-low; + }; + sdc1_on: sdc1-on { clk { pins = "sdc1_clk"; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index e8fd26633d57..c1ba577fc1bc 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -383,6 +384,7 @@ compatible = "qcom,gcc-qcs404"; reg = <0x01800000 0x80000>; #clock-cells = <1>; + #reset-cells = <1>; assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; @@ -411,6 +413,21 @@ #interrupt-cells = <4>; }; + pcie_phy: phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc GCC_PCIE_0_PIPE_ARES>; + reset-names = "phy", "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #phy-cells = <0>; + + status = "disabled"; + }; + sdcc1: sdcc@7804000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x7805000 0x1000>; @@ -777,6 +794,56 @@ status = "disabled"; }; }; + + pcie: pci@10000000 { + compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; + reg = <0x10000000 0xf1d>, + <0x10000f20 0xa8>, + <0x07780000 0x2000>, + <0x10001000 0x2000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ + <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>; + clock-names = "iface", "aux", "master_bus", "slave_bus"; + + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_AHB_ARES>; + reset-names = "axi_m", + "axi_s", + "axi_m_sticky", + "pipe_sticky", + "pwr", + "ahb"; + + phys = <&pcie_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; }; timer {