From patchwork Tue Feb 19 06:04:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 158669 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3296759jaa; Mon, 18 Feb 2019 22:04:03 -0800 (PST) X-Google-Smtp-Source: AHgI3IYhA+RetqQKzp8SainKiFgllfczRDKFhQwHrDuMIsTGfyguwl+s/Tbi9VdBe1yS03oYjRdx X-Received: by 2002:a63:fa10:: with SMTP id y16mr21642947pgh.88.1550556243242; Mon, 18 Feb 2019 22:04:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550556243; cv=none; d=google.com; s=arc-20160816; b=VZQXBfB0Cvla6rUwPJW2yvLV2jcwZkT4akWaMQexWeN4dT5G87ger5JXSgXPuyo5H3 ZqmxH58t9w6WpaqmwwwNHJ+hrCimgqxF5npOrb6304QrUZQrYZ0ctYaihcaSPA0aKL67 usvYmpHzxMa0OXYbIq8WXX50Z4oBG6oiLNOZ5Dy6/vwyrkfwNkQ6GfmkdGK2f/hle9ga P+5qKbVJDp/9RBfeG9b6PMtKXqHp+WVxFMKKxHM65qK6iaNHt+I00vanqMEvcW/OaIqC 2ojrc2spcKXB8/w8piwKlqp7607WijLfGr3neZmnLzW2P9tQ2aSeIAFz3h1T4yPZf+2W kV8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=UHgZWVALJGh9VRwB+6Xb3H1nv3kTvbz3xid7mcSpBgQ=; b=EcRu3ROacUj9k7JTl8KdkKFeEkPc2EEX4Ut+iJdCR0XxHSzvwghjU6fysWx43qLHDQ rUwYpk9G4qtP5rcXGqJyzlyUdmCdjfpmSS7ASHFdAQ9qB3Jt8cq2NvMCvzKkIjd7YyQy uZYb+YMgwuMJZ935EudazfOuTK9vw5DXmeSZXCmxZAkGQyhV+4eUdJBcsQgOlFuTbj21 F/UumTD7oKPSmK0vwQ5vufUIAiL58+HECLy0So766JMfFr8BQJuNKgr74/0yZZ9YGjcw IMcfY2A3+IY3ILpZ8RX9Ly+YMV7ZSsqzMCtCArHFYKfJfZu9kiyUQ9575z8mdOiIBLBO GyiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=evBjV0Rv; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c24si8338714pgw.46.2019.02.18.22.04.03; Mon, 18 Feb 2019 22:04:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=evBjV0Rv; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726869AbfBSGEB (ORCPT + 15 others); Tue, 19 Feb 2019 01:04:01 -0500 Received: from mail-pf1-f193.google.com ([209.85.210.193]:35367 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726763AbfBSGEB (ORCPT ); Tue, 19 Feb 2019 01:04:01 -0500 Received: by mail-pf1-f193.google.com with SMTP id j5so5190028pfa.2 for ; Mon, 18 Feb 2019 22:04:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UHgZWVALJGh9VRwB+6Xb3H1nv3kTvbz3xid7mcSpBgQ=; b=evBjV0Rvbu8ogFMch88cFZ1epBrCxrgc/xj8qB64C4DCnrzYMiBgwRBJ0rRe5YPpvv Ktig9n+k/+vW7Xv9Sr3mP0fM0VHsJwBbvQE0ZqJOU6BTuwcFBAmJCwza+gcGfvWEHG/1 v1RDy81mptRcYcYjvWqPFbEcobxtNflkoI/N+cjAs6A3WphzQTcyXI6G7IKfKzczBCJs ml8voGuBKYOTHVNWrcdCLKcwxmxx9GN0OG/EB9OLSqbJBb0pq7tAPLxxv/cRvOkW+H9j iH71vn3GOzMbI+eewd1O1DL8W9U4ikivx8DLNvEJy419yLvAxdyOsV7Q/FtXzV2hoae2 WiKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UHgZWVALJGh9VRwB+6Xb3H1nv3kTvbz3xid7mcSpBgQ=; b=GlruyxkUgEwB85tQRIp8spLhN4f/6um5mqov69ofc/LUPHh6gx9H1LH1LNhyNJWGdi IDMe51zO30suRsbJpGxsmRaN2W5BOWUDk1BhW25pBGF6KRPnmrl//zBwaH7uQw5IOzrT FJKT/HBa3NLTqgZS0/0pAjFcer6wIRaHb1dO3V7QXURZEXGXp+f3eM8CkKLwbgMlOOtF pyYWx6b2fq/To+kkB1zaBk5EocUjOMaYFtKNliWNvB1nLwISs9IkkSsO11GwURDa5S67 eRdNm20hALaWfJwyo988PCeQzNEiKY7TMFwnJHyTip9Kutky7UA0JySlpxRAOYMB4Pdy e1ew== X-Gm-Message-State: AHQUAuaBxGvGNS+190xnqnbm+Aacj6/4KUNgi38ZXQx+bsw8TecXs+PI fAxT1C93Q4TRQ22r2rK6naweOocWFKk= X-Received: by 2002:a63:8f45:: with SMTP id r5mr22031360pgn.222.1550556239581; Mon, 18 Feb 2019 22:03:59 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id 86sm31914838pfk.157.2019.02.18.22.03.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 Feb 2019 22:03:58 -0800 (PST) From: Bjorn Andersson To: Bjorn Helgaas , Stanimir Varbanov , Lorenzo Pieralisi Cc: Andy Gross , David Brown , Rob Herring , Mark Rutland , Kishon Vijay Abraham I , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 6/7] PCI: qcom: Add QCS404 PCIe controller support Date: Mon, 18 Feb 2019 22:04:06 -0800 Message-Id: <20190219060407.15263-7-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190219060407.15263-1-bjorn.andersson@linaro.org> References: <20190219060407.15263-1-bjorn.andersson@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The QCS404 platform contains a PCIe controller of version 2.4.0 and a Qualcomm PCIe2 PHY. The driver already supports version 2.4.0, for the IPQ4019, but this support touches clocks and resets related to the PHY as well, and there's no upstream driver for the PHY. On QCS404 we must initialize the PHY, so a separate PHY driver is implemented to take care of this and the controller driver is updated to not require the PHY related resources. This is done by relying on the fact that operations in both the clock and reset framework are nops when passed NULL, so we can isolate this change to only the get_resource function. For QCS404 we also need to enable the AHB (iface) clock, in order to access the register space of the controller, but as this is not part of the IPQ4019 DT binding this is only added for new users of the 2.4.0 controller. Reviewed-by: Niklas Cassel Signed-off-by: Bjorn Andersson --- drivers/pci/controller/dwc/pcie-qcom.c | 64 +++++++++++++++----------- 1 file changed, 38 insertions(+), 26 deletions(-) -- 2.18.0 diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index b4d8bcf6eb77..3724ab5de956 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -113,7 +113,7 @@ struct qcom_pcie_resources_2_3_2 { }; struct qcom_pcie_resources_2_4_0 { - struct clk_bulk_data clks[3]; + struct clk_bulk_data clks[4]; int num_clks; struct reset_control *axi_m_reset; struct reset_control *axi_s_reset; @@ -637,13 +637,16 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); int ret; res->clks[0].id = "aux"; res->clks[1].id = "master_bus"; res->clks[2].id = "slave_bus"; + res->clks[3].id = "iface"; - res->num_clks = 3; + /* qcom,pcie-ipq4019 is defined without "iface" */ + res->num_clks = is_ipq ? 3 : 4; ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); if (ret < 0) @@ -657,27 +660,33 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) if (IS_ERR(res->axi_s_reset)) return PTR_ERR(res->axi_s_reset); - res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe"); - if (IS_ERR(res->pipe_reset)) - return PTR_ERR(res->pipe_reset); - - res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev, - "axi_m_vmid"); - if (IS_ERR(res->axi_m_vmid_reset)) - return PTR_ERR(res->axi_m_vmid_reset); - - res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev, - "axi_s_xpu"); - if (IS_ERR(res->axi_s_xpu_reset)) - return PTR_ERR(res->axi_s_xpu_reset); - - res->parf_reset = devm_reset_control_get_exclusive(dev, "parf"); - if (IS_ERR(res->parf_reset)) - return PTR_ERR(res->parf_reset); - - res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); - if (IS_ERR(res->phy_reset)) - return PTR_ERR(res->phy_reset); + if (is_ipq) { + /* + * These resources relates to the PHY or are secure clocks, but + * are controlled here for IPQ4019 + */ + res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe"); + if (IS_ERR(res->pipe_reset)) + return PTR_ERR(res->pipe_reset); + + res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev, + "axi_m_vmid"); + if (IS_ERR(res->axi_m_vmid_reset)) + return PTR_ERR(res->axi_m_vmid_reset); + + res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev, + "axi_s_xpu"); + if (IS_ERR(res->axi_s_xpu_reset)) + return PTR_ERR(res->axi_s_xpu_reset); + + res->parf_reset = devm_reset_control_get_exclusive(dev, "parf"); + if (IS_ERR(res->parf_reset)) + return PTR_ERR(res->parf_reset); + + res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); + if (IS_ERR(res->phy_reset)) + return PTR_ERR(res->phy_reset); + } res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev, "axi_m_sticky"); @@ -697,9 +706,11 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) if (IS_ERR(res->ahb_reset)) return PTR_ERR(res->ahb_reset); - res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb"); - if (IS_ERR(res->phy_ahb_reset)) - return PTR_ERR(res->phy_ahb_reset); + if (is_ipq) { + res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb"); + if (IS_ERR(res->phy_ahb_reset)) + return PTR_ERR(res->phy_ahb_reset); + } return 0; } @@ -1284,6 +1295,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 }, { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 }, { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 }, + { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, { } };