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[86.30.250.44]) by smtp.gmail.com with ESMTPSA id w80sm3739628wme.38.2019.01.29.05.23.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Jan 2019 05:23:54 -0800 (PST) From: Srinivas Kandagatla To: andy.gross@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Jordan Crouse , Vivek Gautam , Srinivas Kandagatla Subject: [PATCH 4/6] arm64: dts: Add Adreno GPU and GPU smmu definitions Date: Tue, 29 Jan 2019 13:23:33 +0000 Message-Id: <20190129132335.30695-5-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190129132335.30695-1-srinivas.kandagatla@linaro.org> References: <20190129132335.30695-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jordan Crouse Add an initial node for the Adreno GPU and it's companion SMMU. The GPU node is mostly complete except for a bare bones power table that will be filled out more completely later. Signed-off-by: Jordan Crouse [Remove mmagic clocks from GPU/smmu nodes] Signed-off-by: Vivek Gautam Signed-off-by: Srinivas Kandagatla --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 52 +++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) -- 2.20.1 diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 0d0b9482aa4d..b5f23594905c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -84,6 +84,12 @@ qcom,client-id = <1>; qcom,vmid = <15>; }; + + zap_shader_region: gpu@8f200000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x90b00000 0x0 0xa00000>; + no-map; + }; }; cpus { @@ -1338,6 +1344,52 @@ }; }; + gpu@b00000 { + compatible = "qcom,adreno-530.2", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0xb00000 0x3f000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&mmcc GPU_GX_GFX3D_CLK>, + <&mmcc GPU_AHB_CLK>, + <&mmcc GPU_GX_RBBMTIMER_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_MMSS_BIMC_GFX_CLK>; + + clock-names = "core", + "iface", + "rbbmtimer", + "mem", + "mem_iface"; + + power-domains = <&mmcc GPU_GDSC>; + iommus = <&adreno_smmu 0>; + + qcom,gpu-quirk-two-pass-use-wfi; + qcom,gpu-quirk-fault-detect-mask; + + /* This is a safe speed for bring up in all bin levels. + * This isn't the fastest the chip can go, but we can + * get there eventually */ + qcom,gpu-pwrlevels { + compatible = "qcom,gpu-pwrlevels"; + qcom,gpu-pwrlevel@0 { + qcom,gpu-freq = <510000000>; + }; + qcom,gpu-pwrlevel@1 { + qcom,gpu-freq = <27000000>; + }; + }; + + zap-shader { + memory-region = <&zap_shader_region>; + }; + }; + mdss: mdss@900000 { compatible = "qcom,mdss";