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[209.132.180.67]) by mx.google.com with ESMTP id f12-v6si3788339plo.91.2018.03.06.04.33.34; Tue, 06 Mar 2018 04:33:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jDCFY4TY; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932629AbeCFMdd (ORCPT + 10 others); Tue, 6 Mar 2018 07:33:33 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:42103 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932613AbeCFMdc (ORCPT ); Tue, 6 Mar 2018 07:33:32 -0500 Received: by mail-wr0-f195.google.com with SMTP id k9so20727036wre.9 for ; Tue, 06 Mar 2018 04:33:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=ifqo2ZQT0S5f9Bu7SpNpElEgnqdsehFZyEppoclzGR0=; b=jDCFY4TYRO6GYERRDpfkJ4Wg7avztoO/wWzwGuNf0V7t+dMZWPWYv5IfeHFOa0J2da XmHaI1KqW86g9YML+wWJbffhWvVKKKA/y3GwcvkEZCC9Pl4j7ldDf1k8Ro3eWPJ14Fnb 3vT4UpFKDPNZmG4ZBOO774aBQsTbLI4TjHhlo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ifqo2ZQT0S5f9Bu7SpNpElEgnqdsehFZyEppoclzGR0=; b=FuQbQTSEQJ8couBsUajyKpBGaIcgHl33BbZ5fQ2E0+U+IgToF6mrxVQYCyd9v4sBuw v3gwrwB+XJ9ZmuPvXEwCI2YBtDNsBKxYf7bckWYqidAiTUtg6bm6gLBPg/28ainVwfsB UuNQVkpB9WrVfQ1tup+LJrhAezs+ugfTyO+3pojcNLWOewPSAAoBn6xc3Ui6wKqI3BrR Pb2NwD7Yx998AhjBTXCHClnVHu4WRoGQIkmSBjslJXlTUN4jnXGb9gdm6SL/Y+E0i1Gf XkDNQVLp12Dxgcc42SiGwAUuuyqYAlinxFh6/B3SBeQ34P7bTCHEvedjo956wUKkgWva W/Zw== X-Gm-Message-State: APf1xPD/ncmo2csLZcLg+B30cqBmWW4i9TlzAF/N9ZA5cI9O9xYxWF7O Iy+o4lTlGpr8Mi1CKZj/TzJlGg== X-Received: by 10.223.134.42 with SMTP id 39mr16729504wrv.10.1520339611442; Tue, 06 Mar 2018 04:33:31 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.94.213]) by smtp.gmail.com with ESMTPSA id y75sm11590514wme.13.2018.03.06.04.33.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Mar 2018 04:33:30 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: andy.gross@linaro.org, david.brown@linaro.org, bjorn.andersson@linaro.org, arnd@arndb.de, akdwived@codeaurora.org, nicolas.dechesne@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-kernel@vger.kernel.or, arnaud.pouliquen@st.com, Benjamin Gaignard Subject: [RESEND] firmware: qcom_scm: use correct parameter type for dma_alloc_coherent Date: Tue, 6 Mar 2018 13:33:20 +0100 Message-Id: <20180306123320.24523-1-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Benjamin Gaignard dma_alloc_coherent expects it third argument type to be dma_addr_t and not phys_addr_t. When phys_addr_t is defined as u32 and dma_addr_t as u64 that generate a compilation issue. Change the variable name because dma_alloc_coherent returns a bus address not a physical address. Fixes: d82bd359972a7 ("firmware: scm: Add new SCM call API for switching memory ownership") Signed-off-by: Benjamin Gaignard --- drivers/firmware/qcom_scm.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 5a7d693009ef..2847f9a93cfe 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -448,7 +448,7 @@ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, struct qcom_scm_mem_map_info *mem_to_map; phys_addr_t mem_to_map_phys; phys_addr_t dest_phys; - phys_addr_t ptr_phys; + dma_addr_t handle; size_t mem_to_map_sz; size_t dest_sz; size_t src_sz; @@ -466,7 +466,7 @@ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(dest_sz, SZ_64); - ptr = dma_alloc_coherent(__scm->dev, ptr_sz, &ptr_phys, GFP_KERNEL); + ptr = dma_alloc_coherent(__scm->dev, ptr_sz, &handle, GFP_KERNEL); if (!ptr) return -ENOMEM; @@ -480,14 +480,14 @@ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, /* Fill details of mem buff to map */ mem_to_map = ptr + ALIGN(src_sz, SZ_64); - mem_to_map_phys = ptr_phys + ALIGN(src_sz, SZ_64); + mem_to_map_phys = handle + ALIGN(src_sz, SZ_64); mem_to_map[0].mem_addr = cpu_to_le64(mem_addr); mem_to_map[0].mem_size = cpu_to_le64(mem_sz); next_vm = 0; /* Fill details of next vmid detail */ destvm = ptr + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64); - dest_phys = ptr_phys + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64); + dest_phys = handle + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64); for (i = 0; i < dest_cnt; i++) { destvm[i].vmid = cpu_to_le32(newvm[i].vmid); destvm[i].perm = cpu_to_le32(newvm[i].perm); @@ -497,8 +497,8 @@ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, } ret = __qcom_scm_assign_mem(__scm->dev, mem_to_map_phys, mem_to_map_sz, - ptr_phys, src_sz, dest_phys, dest_sz); - dma_free_coherent(__scm->dev, ALIGN(ptr_sz, SZ_64), ptr, ptr_phys); + handle, src_sz, dest_phys, dest_sz); + dma_free_coherent(__scm->dev, ALIGN(ptr_sz, SZ_64), ptr, handle); if (ret) { dev_err(__scm->dev, "Assign memory protection call failed %d.\n", ret);