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[209.132.180.67]) by mx.google.com with ESMTP id z15si9927093pgc.358.2017.05.15.00.50.33; Mon, 15 May 2017 00:50:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759633AbdEOHub (ORCPT + 10 others); Mon, 15 May 2017 03:50:31 -0400 Received: from mail-wm0-f50.google.com ([74.125.82.50]:36484 "EHLO mail-wm0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756679AbdEOHu3 (ORCPT ); Mon, 15 May 2017 03:50:29 -0400 Received: by mail-wm0-f50.google.com with SMTP id u65so71752795wmu.1 for ; Mon, 15 May 2017 00:50:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=BMolIRVz9s91YULE+N02XJVf+WEYAfW3f+x1NCUFCSY=; b=LYf4Rzv9ROIzohYVnBw/t1Diy79M/ILXCEgkAJlLL91qy6mf4ay6vcNwslKbHrRZHb ZIDhBB+GY46Jh70fH+1bs36/B8sPBc/5u/03tJcIzQSJHyVkT6hD5Ig17januKVt91Zk 0kdYcjIJmanl6yKsJXKQduETPKvLd9vAiHZLQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=BMolIRVz9s91YULE+N02XJVf+WEYAfW3f+x1NCUFCSY=; b=B5xPl8YGDdtESpmcHnh8pCGQN/NzyuOyEAOfASUZ+Jo+SmBj+oBl5IpFxH69C8Z/ZK 7G/ItkqkByfBzleW5CDA8mrqjtSZR/rFMZlHTDEWQfD05DsA3TtVZQ25i/Tzx+OZDWz3 13uGu+rtjl0yLhDrcggP9e9/Ajuw1+vAN9eB26bcViROw6lO0y4kAZHBX0gZ0HhDKJ4s Q+A22xCG9Nw94ZRJuv6ErTRt16Kzhiwtuz0w87h6d6NS6dZjukaSLOZOsH6oyxSy/45O Aj1aOnnsLsYk9sMsw9wR0GrRYQxSyXPzLXBumV5ruCSM+KAkaXcU5GPOl12fesAqrxP9 H9NQ== X-Gm-Message-State: AODbwcB65GxmMVgwX0aBOcOUljRcMWfzUSOWDhAYSSw0SOdWVfCJyp9o b6wH8irhlYLqto9e X-Received: by 10.25.23.210 with SMTP id 79mr1520139lfx.158.1494834617948; Mon, 15 May 2017 00:50:17 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id l135sm1996440lfb.43.2017.05.15.00.50.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 May 2017 00:50:16 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Andy Gross , Bjorn Andersson Cc: Stephen Boyd , Linus Walleij Subject: [PATCH 1/2] ARM: dts: add GSBI8 defines to the MSM8660 family Date: Mon, 15 May 2017 09:50:12 +0200 Message-Id: <20170515075012.3696-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.3 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This defines the memory location and interrupt used by the GSBI8 I2C adapter on the MSM8660 SoCs. We add it as "disabled" by default so that boards using this I2C can enable it. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/qcom-msm8660.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) -- 2.9.3 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Bjorn Andersson diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 747669a62aa8..a53c0f9970bd 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -107,6 +107,31 @@ reg = <0x900000 0x4000>; }; + + gsbi8: gsbi@19800000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x19800000 0x100>; + clocks = <&gcc GSBI8_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi8_i2c: i2c@19880000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x19880000 0x1000>; + interrupts = <0 161 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + gsbi12: gsbi@19c00000 { compatible = "qcom,gsbi-v1.0.0"; cell-index = <12>;