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[209.132.180.67]) by mx.google.com with ESMTP id y15si1543986plh.90.2017.03.15.02.17.18; Wed, 15 Mar 2017 02:17:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751856AbdCOJRB (ORCPT + 9 others); Wed, 15 Mar 2017 05:17:01 -0400 Received: from mail-lf0-f47.google.com ([209.85.215.47]:33947 "EHLO mail-lf0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751694AbdCOJQ7 (ORCPT ); Wed, 15 Mar 2017 05:16:59 -0400 Received: by mail-lf0-f47.google.com with SMTP id z15so4220519lfd.1 for ; Wed, 15 Mar 2017 02:16:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=SL/zaFU6wLq45vOEJaSXrwKxoDiLJ5jWp8F9E5AbebI=; b=HdGj0iN9Lqtm/2iQCcQ1sVfb3YD+SHk95QglYzr3mWi69C+6YK041pqPCj+41k3Izd 0ZEzQhCICeuE2JsBVHL327p6WER9rOCWVPl7Y++TPgFCPoL4gpBiRyGdSsE/Qvlavlvq 2WUHhpJYVuBlvvgzOog2itH/GWsZRYAZZeq4U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=SL/zaFU6wLq45vOEJaSXrwKxoDiLJ5jWp8F9E5AbebI=; b=msJJQ6ryYrX+CNYYMsLA6yWotPqQQBghIrSOGSAUc4EUxus5sg1jx5qacBOnsJOg4i OfYxcsVWuROoVXLK03WLPLwmWaFS5vDo1JqVRbCVrFlK9ps/HPcp3v/NHNUy3fINBSta RwdWjE83XNpDUflZyGkLqkCCgch4RoXy42beNe3e0MkJPbLSKyc2NzHq0Gox9FmCVhi4 PZfsi18UZrjD80bIABRKjE7w6Z0C+cZyl70G2x3xFAKaLK3OVWFWDsmvm5Sa4HNwrQ+5 yBxIQEQ4i5eKgajdjYPjcjwskNjFd1QHK07mFnfw3kvwHAj+hn43X6YjdykvQrZXM+sT nGWw== X-Gm-Message-State: AFeK/H2nftgJkbcTrPe02ggri/TJxNmjncq5ufQy6PLxmgdAuCC9D+NCMVb/uNSjLYcmzRZ5 X-Received: by 10.25.76.194 with SMTP id z185mr695200lfa.183.1489569417479; Wed, 15 Mar 2017 02:16:57 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id j6sm219392lfg.60.2017.03.15.02.16.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 15 Mar 2017 02:16:55 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Andy Gross , Bjorn Andersson Cc: Stephen Boyd , David Brown , Linus Walleij Subject: [PATCH 1/2] ARM: dts: add SDC2 and SDC4 to the MSM8660 family Date: Wed, 15 Mar 2017 10:16:49 +0100 Message-Id: <20170315091649.7495-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.3 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org To make the picture complete, add DTS entries also for the second and fourth MMC/SD blocks on the MSM8660. SDC2 is an 8-bit interface and SDC4 is a 4-bit interface. Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Drop non-removable this is a board-specific attribute. --- arch/arm/boot/dts/qcom-msm8660.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) -- 2.9.3 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 91c9a62ae725..747669a62aa8 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -392,6 +392,21 @@ cap-mmc-highspeed; }; + sdcc2: sdcc@12140000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12140000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + }; + sdcc3: sdcc@12180000 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; @@ -408,6 +423,21 @@ no-1-8-v; }; + sdcc4: sdcc@121c0000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x121c0000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + max-frequency = <48000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + }; + sdcc5: sdcc@12200000 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>;