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[209.132.180.67]) by mx.google.com with ESMTP id 68si18400474pfa.203.2017.03.06.00.27.07; Mon, 06 Mar 2017 00:27:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752580AbdCFI1G (ORCPT + 9 others); Mon, 6 Mar 2017 03:27:06 -0500 Received: from mail-wm0-f44.google.com ([74.125.82.44]:37748 "EHLO mail-wm0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752716AbdCFI1F (ORCPT ); Mon, 6 Mar 2017 03:27:05 -0500 Received: by mail-wm0-f44.google.com with SMTP id n11so57646737wma.0 for ; Mon, 06 Mar 2017 00:26:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=ZYTQbszPnBKVyZWoQRJ5/kkaiU/adsPYq1ho+T17JtU=; b=i+lqDLhxNELj9QSWnZ8Cllq9prFvWHwYp3u0m8BQsQ14iayj2P9dSl9hBbB0K/4z1V LBwzWyBEckbZad3P3B8465u+P2l42GzsdjOpJhEzlALDwdK192y5Zd+JCyHixeW+6KT9 1BHBpzH5vXHmw08UXt3VHTXflbLi6s8w8M9BE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ZYTQbszPnBKVyZWoQRJ5/kkaiU/adsPYq1ho+T17JtU=; b=m9uKGd0Zhrs1ye+QhLPsmwazo8fJwWzA67Wt9wM8+DyOBHPFyMrVWSQ2mBQmC/gj11 HHIB3twIu5ejpuAAPah7AaJ4uvpoY2fIvITRSSej2zg50zV1+cMliO4HYKnrczLQuLLF ccMlIcfRMzfosjkRb2slrhLqG6hJO7CYe6JqLU5j8oJ6qJdMvXxbOzf1KlgLv3lcD3HG NO54us1FTdPYLMfjmwClZiaVnK9HKvXMvGjBQU3ZOF8xzPregjrTKxJo1b+jHahpxsaY N//bEW6vczRRrngTJIdoiQjIuqwDPGEfs0o/tedQ2g2fPUw+JiEvdhxiQAkHqHZHp03d Cmwg== X-Gm-Message-State: AMke39nX/BSD0rr7eOio45KCj6+I9X21Xvh3siIohL7vqkw7E00fRb/wWlSk8ky4bmJXSzWb X-Received: by 10.28.194.7 with SMTP id s7mr448154wmf.136.1488787234890; Mon, 06 Mar 2017 00:00:34 -0800 (PST) Received: from genomnajs.c.hoisthospitality.com ([109.74.56.122]) by smtp.gmail.com with ESMTPSA id x193sm13707475wme.23.2017.03.06.00.00.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 Mar 2017 00:00:33 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Andy Gross , Bjorn Andersson Cc: Stephen Boyd , David Brown , Linus Walleij Subject: [PATCH 1/2] ARM: dts: add SDC2 and SDC4 to the MSM8660 family Date: Mon, 6 Mar 2017 09:00:29 +0100 Message-Id: <20170306080029.3422-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.3 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org To make the picture complete, add DTS entries also for the second and fourth MMC/SD blocks on the MSM8660. SDC2 is an 8-bit interface and SDC4 is a 4-bit interface. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/qcom-msm8660.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) -- 2.9.3 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Bjorn Andersson diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 91c9a62ae725..5564ad131325 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -392,6 +392,22 @@ cap-mmc-highspeed; }; + sdcc2: sdcc@12140000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12140000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + }; + sdcc3: sdcc@12180000 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; @@ -408,6 +424,21 @@ no-1-8-v; }; + sdcc4: sdcc@121c0000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x121c0000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + }; + sdcc5: sdcc@12200000 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>;