From patchwork Sat Sep 9 20:16:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Ojha X-Patchwork-Id: 721238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73DABEE14C3 for ; Sat, 9 Sep 2023 20:42:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231830AbjIIUmJ (ORCPT ); Sat, 9 Sep 2023 16:42:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231269AbjIIUmI (ORCPT ); Sat, 9 Sep 2023 16:42:08 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9376E19E; Sat, 9 Sep 2023 13:42:04 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 389KJIBh030508; Sat, 9 Sep 2023 20:19:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=ACXZo6SoFenqElAwh1aLmZnN6nH9EA+30CpBcrvZiOI=; b=Rt1gP1l5mXVAmq1hgjVY/pRMA+ogMvFXupVoxzTo2LeeTfwyJbn0NlPcJeja6I1bfxmK xUW659AMsZLMxg+V/8s5rxA7r9Kiim2F3BwpiPz9v5WlM22ti2Ap3bSdWd/TEWwwY0QE dyoO+JlkguQN/QYFtLiKjN/Vv1iwzd2BTNu3h8Ydpf7G18p9iumyco5iAyCgctij1Bjc 3vxOVaxmxqqlSKhyWx6WK9XinUfgFw+rqm6YEyoa3VtT1EGFCKd9WWcYw3VJQ6+Nml8q V7KrhKirTwHYHhBuwBqY0tuBp7rTP+7lDeEuvFwJ1QKnR61KVzqgDRTK2ZXGfSSlopsX 5Q== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3t0edmh6se-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 09 Sep 2023 20:19:18 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 389KIxVf024061 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 9 Sep 2023 20:18:59 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Sat, 9 Sep 2023 13:18:48 -0700 From: Mukesh Ojha To: , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v5 15/17] firmware: scm: Modify only the download bits in TCSR register Date: Sun, 10 Sep 2023 01:46:16 +0530 Message-ID: <1694290578-17733-16-git-send-email-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1694290578-17733-1-git-send-email-quic_mojha@quicinc.com> References: <1694290578-17733-1-git-send-email-quic_mojha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: mf2Som43FWD0w6bnaWgCvn2IUOBI5APA X-Proofpoint-GUID: mf2Som43FWD0w6bnaWgCvn2IUOBI5APA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-09_19,2023-09-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 malwarescore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309090188 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Crashdump collection is based on the DLOAD bit of TCSR register. To retain other bits, we read the register and modify only the DLOAD bit as the other bits have their own significance. Co-developed-by: Poovendhan Selvaraj Signed-off-by: Mukesh Ojha Tested-by: Kathiravan Thirumoorthy # IPQ9574 --- drivers/firmware/qcom_scm.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 5ea8fc4fd4e8..eda92f713019 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -5,6 +5,8 @@ #include #include #include +#include +#include #include #include #include @@ -30,6 +32,10 @@ module_param(download_mode, bool, 0); #define SCM_HAS_IFACE_CLK BIT(1) #define SCM_HAS_BUS_CLK BIT(2) +#define QCOM_DLOAD_MASK GENMASK(5, 4) +#define QCOM_DLOAD_FULLDUMP 0x1 +#define QCOM_DLOAD_NODUMP 0x0 + struct qcom_scm { struct device *dev; struct clk *core_clk; @@ -444,6 +450,7 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) static void qcom_scm_set_download_mode(bool enable) { + u32 val = enable ? QCOM_DLOAD_FULLDUMP : QCOM_DLOAD_NODUMP; bool avail; int ret = 0; @@ -453,8 +460,9 @@ static void qcom_scm_set_download_mode(bool enable) if (avail) { ret = __qcom_scm_set_dload_mode(__scm->dev, enable); } else if (__scm->dload_mode_addr) { - ret = qcom_scm_io_writel(__scm->dload_mode_addr, - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); + ret = qcom_scm_io_update_field(__scm->dload_mode_addr, + QCOM_DLOAD_MASK, + FIELD_PREP(QCOM_DLOAD_MASK, val)); } else { dev_err(__scm->dev, "No available mechanism for setting download mode\n");