From patchwork Mon Aug 28 19:18:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan R X-Patchwork-Id: 717777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C58D4C83F1F for ; Mon, 28 Aug 2023 19:20:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233364AbjH1TT7 (ORCPT ); Mon, 28 Aug 2023 15:19:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233362AbjH1TTn (ORCPT ); Mon, 28 Aug 2023 15:19:43 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52AA2107; Mon, 28 Aug 2023 12:19:40 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37SJGW7a013107; Mon, 28 Aug 2023 19:19:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=nPYs6hFoo6E7/FWcrbdC3FBYvedtX/7cz7YBcPZkCtI=; b=igsPpzXRi7zsoQJPtsbVXMROdkbeFJHh1DvZJmcGCgOJ2kRFixmYKHKnjMRflWC6i8Bs JT684VVrhD/2RHlMV0I41JmCKSB3TLjz8Eq28rVGkjKPJzq1FcyICUKdoYxEaUMvQz+B Ww9+g5p43nUGq2B6MEt4DJAO1yavBcokbjJ2AGI/xPgSrH6AM/EnvkuyP6dYgDCZykSc QRt5pBU63JZi8bJ7ONWM4IMcWGnnnKJsvg+mS8Q0imi0LGu0Itb/klrFkBmovmR1u7Fy oh2LfKDj0JZfnc8t/1MpNTJ2puoQZz51DZxA5N/hKZ/sca/rq+0u82kZpkmzFz05Spa5 Lw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3sqapfmfhd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Aug 2023 19:19:30 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 37SJJTn0003302 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Aug 2023 19:19:29 GMT Received: from srichara-linux.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Mon, 28 Aug 2023 12:19:00 -0700 From: Sricharan Ramabadhran To: , , , , , , , , , , , , , , Subject: [PATCH 3/7] thermal/drivers/qcom/tsens: Add support for IPQ5018 tsens Date: Tue, 29 Aug 2023 00:48:23 +0530 Message-ID: <1693250307-8910-4-git-send-email-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1693250307-8910-1-git-send-email-quic_srichara@quicinc.com> References: <1693250307-8910-1-git-send-email-quic_srichara@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: GTjzH62Dk5iep0RkRZTO-vxl5gTVq0ih X-Proofpoint-GUID: GTjzH62Dk5iep0RkRZTO-vxl5gTVq0ih X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-28_16,2023-08-28_04,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 mlxscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 adultscore=0 spamscore=0 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308280168 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ5018 has tsens IP V1.0, 4 sensors and 1 interrupt. The soc does not have a RPM, hence tsens has to be reset and enabled in the driver init. Adding the driver support for same. Signed-off-by: Sricharan Ramabadhran --- drivers/thermal/qcom/tsens-v1.c | 115 ++++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.h | 2 +- 2 files changed, 116 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index dc1c4ae2d8b0..a74dae69408b 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -42,6 +42,59 @@ static struct tsens_legacy_calibration_format tsens_qcs404_nvmem = { }, }; +struct tsens_legacy_calibration_format tsens_ipq5018_nvmem = { + .base_len = 8, + .base_shift = 2, + .sp_len = 6, + .mode = { 0, 8 }, + .invalid = { 0, 2 }, + .base = { { 0, 11 }, { 0, 19 } }, + .sp = { + { { 0, 27 }, { 1, 1 } }, + { { 1, 7 }, { 1, 13 } }, + { { 1, 19 }, { 1, 25 } }, + { { 1, 31 }, { 2, 5 } }, + { { 2, 11 }, { 3, 0 } }, + }, +}; + +static void fixup_ipq5018_points(int mode, u32 *p1, u32 *p2) +{ + if (mode == NO_PT_CALIB) { + p1[0] = 403; + p2[0] = 688; + p1[1] = 390; + p2[1] = 674; + p1[2] = 341; + p2[2] = 635; + p1[3] = 387; + p2[3] = 673; + p1[4] = 347; + p2[4] = 639; + } +} + +static int calibrate_ipq5018(struct tsens_priv *priv) +{ + u32 p1[10], p2[10]; + u32 *qfprom_cdata; + int mode; + + qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); + if (IS_ERR(qfprom_cdata)) + return PTR_ERR(qfprom_cdata); + + mode = tsens_read_calibration_legacy(priv, &tsens_ipq5018_nvmem, + p1, p2, + qfprom_cdata, NULL); + + fixup_ipq5018_points(mode, p1, p2); + compute_intercept_slope(priv, p1, p2, mode); + kfree(qfprom_cdata); + + return 0; +} + static int calibrate_v1(struct tsens_priv *priv) { u32 p1[10], p2[10]; @@ -79,6 +132,18 @@ static struct tsens_features tsens_v1_feat = { .trip_max_temp = 120000, }; +static struct tsens_features tsens_v1_ipq5018_feat = { + .ver_major = VER_1_X, + .crit_int = 0, + .combo_int = 0, + .adc = 1, + .srot_split = 1, + .max_sensors = 11, + .trip_min_temp = -40000, + .trip_max_temp = 120000, + .no_early_init = 1, +}; + static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { /* ----- SROT ------ */ /* VERSION */ @@ -150,6 +215,43 @@ static int __init init_8956(struct tsens_priv *priv) { return init_common(priv); } +static int init_ipq5018(struct tsens_priv *priv) +{ + int ret; + u32 mask; + + init_common(priv); + if (!priv->tm_map) + return -ENODEV; + + ret = regmap_field_write(priv->rf[TSENS_SW_RST], 1); + if (ret) { + dev_err(priv->dev, "Reset failed\n"); + return ret; + } + + mask = GENMASK(10, 0); + ret = regmap_field_update_bits(priv->rf[SENSOR_EN], mask, mask); + if (ret) { + dev_err(priv->dev, "Sensor Enable failed\n"); + return ret; + } + + ret = regmap_field_write(priv->rf[TSENS_EN], 1); + if (ret) { + dev_err(priv->dev, "Enable failed\n"); + return ret; + } + + ret = regmap_field_write(priv->rf[TSENS_SW_RST], 0); + if (ret) { + dev_err(priv->dev, "Reset failed\n"); + return ret; + } + + return 0; +} + static const struct tsens_ops ops_generic_v1 = { .init = init_common, .calibrate = calibrate_v1, @@ -187,3 +289,16 @@ struct tsens_plat_data data_8976 = { .feat = &tsens_v1_feat, .fields = tsens_v1_regfields, }; + +const struct tsens_ops ops_ipq5018 = { + .init = init_ipq5018, + .calibrate = calibrate_ipq5018, + .get_temp = get_temp_tsens_valid, +}; + +struct tsens_plat_data data_ipq5018 = { + .num_sensors = 5, + .ops = &ops_ipq5018, + .feat = &tsens_v1_ipq5018_feat, + .fields = tsens_v1_regfields, +}; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index fb73e3dd0de9..5f0bdbeedf90 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -645,7 +645,7 @@ extern struct tsens_plat_data data_8960; extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, data_8974, data_9607; /* TSENS v1 targets */ -extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956; +extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956, data_ipq5018; /* TSENS v2 targets */ extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;