From patchwork Mon Aug 28 19:18:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan R X-Patchwork-Id: 717779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C7B6C83F12 for ; Mon, 28 Aug 2023 19:20:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233380AbjH1TTz (ORCPT ); Mon, 28 Aug 2023 15:19:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233357AbjH1TTm (ORCPT ); Mon, 28 Aug 2023 15:19:42 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C95A102; Mon, 28 Aug 2023 12:19:40 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37SJCrux001880; Mon, 28 Aug 2023 19:19:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=h/ijjqmHPE8Fyn8GCLvPxjWfXBnR1PvR0zf7ATuDV2o=; b=mJ+YAVlIm4hbnfo1vseMwHQDpytEZAmN6lB/fd8vKCE6F0MloPC2Eee1hSHzZq3drXot Psy58pyXYYNV13xVMfUovA1r1PFCKs2aHlmv7TwPqhFbt5k3uxRXZLcGorkmjKv1VCRL lVhDc90v3/uFWCivGRfghOFrtuwaLnJYiJ2dKkEZXe6ZAn81vnQ/F2nTEQ48sCU3rzSx vdCRlC+6+CA2PEv24xfWtaBO/CrW7L0+RczTpAkJvszLlVw5QSXeWXxivOrYza3pbpDL jVUVrPePg8CXOrovcAeGhp0IokPuxWP+nHZq4QZQUCGfSe1qOUjFZt3DNPMkG/224/I8 ew== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3srvr80t5t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Aug 2023 19:19:29 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 37SJJTmx003302 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Aug 2023 19:19:29 GMT Received: from srichara-linux.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Mon, 28 Aug 2023 12:18:55 -0700 From: Sricharan Ramabadhran To: , , , , , , , , , , , , , , Subject: [PATCH 2/7] thermal/drivers/qcom: Add new feat for soc without rpm Date: Tue, 29 Aug 2023 00:48:22 +0530 Message-ID: <1693250307-8910-3-git-send-email-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1693250307-8910-1-git-send-email-quic_srichara@quicinc.com> References: <1693250307-8910-1-git-send-email-quic_srichara@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: AgHAFsIOKbtt4c6WKE5EGbtSDlLzWqgK X-Proofpoint-ORIG-GUID: AgHAFsIOKbtt4c6WKE5EGbtSDlLzWqgK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-28_16,2023-08-28_04,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 mlxlogscore=999 spamscore=0 clxscore=1015 impostorscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 mlxscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308280168 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some of the tsens IP like the one in IPQ5018 does not have a RPM in the soc. Hence the early init to enable tsens would not be done. So add a flag for that in feat and skip enable checks. Signed-off-by: Sricharan Ramabadhran --- drivers/thermal/qcom/tsens.c | 2 +- drivers/thermal/qcom/tsens.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 98c356acfe98..f39495b61952 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -974,7 +974,7 @@ int __init init_common(struct tsens_priv *priv) ret = regmap_field_read(priv->rf[TSENS_EN], &enabled); if (ret) goto err_put_device; - if (!enabled) { + if (!enabled && !(priv->feat->no_early_init)) { dev_err(dev, "%s: device not enabled\n", __func__); ret = -ENODEV; goto err_put_device; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 2805de1c6827..fb73e3dd0de9 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -505,6 +505,8 @@ enum regfield_ids { * @srot_split: does the IP neatly splits the register space into SROT and TM, * with SROT only being available to secure boot firmware? * @has_watchdog: does this IP support watchdog functionality? + * @no_early_init: does this IP reside in a soc that does not have rpm to + * do pre-init. * @max_sensors: maximum sensors supported by this version of the IP * @trip_min_temp: minimum trip temperature supported by this version of the IP * @trip_max_temp: maximum trip temperature supported by this version of the IP @@ -516,6 +518,7 @@ struct tsens_features { unsigned int adc:1; unsigned int srot_split:1; unsigned int has_watchdog:1; + unsigned int no_early_init:1; unsigned int max_sensors; int trip_min_temp; int trip_max_temp;