@@ -245,6 +245,14 @@
status = "okay";
};
+&pcie_ep {
+ pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default
+ &pcie_ep_wake_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
&pcie_phy {
vdda-phy-supply = <&vreg_l1b_1p2>;
vdda-pll-supply = <&vreg_l4b_0p88>;
@@ -277,6 +285,29 @@
status = "okay";
};
+&tlmm {
+ pcie_ep_clkreq_default: pcie-ep-clkreq-default-state {
+ pins = "gpio56";
+ function = "pcie_clkreq";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie_ep_perst_default: pcie-ep-perst-default-state {
+ pins = "gpio57";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ pcie_ep_wake_default: pcie-ep-wake-default-state {
+ pins = "gpio53";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
&usb {
status = "okay";
};
Enable PCIe Endpoint controller on the SDX65 MTP board based on Qualcomm SDX65 platform. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)