From patchwork Wed Mar 8 12:19:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 661871 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DD2EC6FD1F for ; Wed, 8 Mar 2023 12:20:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231344AbjCHMU1 (ORCPT ); Wed, 8 Mar 2023 07:20:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231297AbjCHMUX (ORCPT ); Wed, 8 Mar 2023 07:20:23 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EE439B2E4; Wed, 8 Mar 2023 04:20:16 -0800 (PST) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 328AupLa008976; Wed, 8 Mar 2023 12:20:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=LXSVFmBozi4uAJpU4s+IRy8bs2gfiPkQFuFlnZemxkw=; b=X7JyIN/ksyyv+vmPnOQlOUIrZ3djr38Be/yoeEyUsa1tB8jyFlxrdkEAEFZbV/WqmiOH aShH2Sh5D/iYiK86h3Eapy6rc18XD99HSffkvtAjOvQIXTub8q1+F7xmNDe0N1R69qx4 d+jROhuvkymcYuAOE+cZ56q6R2+AKd1HWUQLfE+rVVBsB0GPiqR/hdwRB21QAOEu4O+/ C9XPV4KPajln2nkay9QweZQpdlpbasnJKTyISOtCyE/9eTHr9ywUh7rlt1g3+uVrfZb5 bm6yns0w5SBGcqpvvs7c8pgqMW04g4BiaGgGhz+nlQEC1areL5UFe2Ihw4XmGOV7m4BR 4w== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3p6fmm1hq5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 08 Mar 2023 12:20:09 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 328CK6Te031436; Wed, 8 Mar 2023 12:20:06 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3p4fgkn0c9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 08 Mar 2023 12:20:06 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 328CK5xO031430; Wed, 8 Mar 2023 12:20:05 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.213.106.138]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 328CK5c9031422; Wed, 08 Mar 2023 12:20:05 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id E19094FAE; Wed, 8 Mar 2023 17:50:04 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, lee@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 4/6] ARM: dts: qcom: sdx65: Add support for PCIe EP Date: Wed, 8 Mar 2023 17:49:51 +0530 Message-Id: <1678277993-18836-5-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1678277993-18836-1-git-send-email-quic_rohiagar@quicinc.com> References: <1678277993-18836-1-git-send-email-quic_rohiagar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: EkkDcIfw-EwCBTZALwS3zidkfhf3LPAH X-Proofpoint-ORIG-GUID: EkkDcIfw-EwCBTZALwS3zidkfhf3LPAH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-08_07,2023-03-08_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 mlxscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 mlxlogscore=974 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303080106 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for PCIe Endpoint controller on the Qualcomm SDX65 platform. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 59 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index df9d428..5ea6a5a 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -293,6 +294,59 @@ status = "disabled"; }; + pcie_ep: pcie-ep@1c00000 { + compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40200000 0x100000>, + <0x01c03000 0x3000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep", + "ref"; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + pcie_phy: phy@1c06000 { compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; reg = <0x01c06000 0x2000>; @@ -332,6 +386,11 @@ #hwlock-cells = <1>; }; + tcsr: syscon@1fcb000 { + compatible = "qcom,sdx65-tcsr", "syscon"; + reg = <0x01fc0000 0x1000>; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>;