From patchwork Mon Apr 25 11:44:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sankeerth Billakanti \(QUIC\)" X-Patchwork-Id: 565752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A575C433EF for ; Mon, 25 Apr 2022 11:46:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241735AbiDYLtL (ORCPT ); Mon, 25 Apr 2022 07:49:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238987AbiDYLtG (ORCPT ); Mon, 25 Apr 2022 07:49:06 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF83F289BC; Mon, 25 Apr 2022 04:45:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1650887137; x=1682423137; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Qnj3SyhLLaXfmPzPA+zkwNWdJ+d+Aa4qqr65H2FSVXA=; b=EAknslpBh/kGNGG0hYa6blq1cUrJXGaOAHHRrhCc/CoC/O1MGPMcK5Ig I0omAsc+ntuz41YacnHcnMxzWRr+L0JZcwqivSGA/DZmIkplIcgxT7T9H 8DWQ1VIz4xrjosLiq2O4vkMPI74X9XuKpvqejeVusrEDnBC4foH7fFv1f U=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 25 Apr 2022 04:45:36 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2022 04:45:36 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 25 Apr 2022 04:45:35 -0700 Received: from sbillaka-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 25 Apr 2022 04:45:29 -0700 From: Sankeerth Billakanti To: , , , , CC: Sankeerth Billakanti , , , , , , , , , , , , , , , Subject: [PATCH v10 4/4] drm/msm/dp: Support the eDP modes given by panel Date: Mon, 25 Apr 2022 17:14:32 +0530 Message-ID: <1650887072-16652-5-git-send-email-quic_sbillaka@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1650887072-16652-1-git-send-email-quic_sbillaka@quicinc.com> References: <1650887072-16652-1-git-send-email-quic_sbillaka@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The eDP controller does not have a reliable way keep panel powered on to read the sink capabilities. So, the controller driver cannot validate if a mode can be supported by the source. We will rely on the panel driver to populate only the supported modes for now. Signed-off-by: Sankeerth Billakanti Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd --- Changes in v10: - none Changes in v9: - none Changes in v8: - add the drm/msm/dp tag in the commit title drivers/gpu/drm/msm/dp/dp_display.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index fd1dddb9..637fb63 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -998,6 +998,14 @@ enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge, return -EINVAL; } + /* + * The eDP controller currently does not have a reliable way of + * enabling panel power to read sink capabilities. So, we rely + * on the panel driver to populate only supported modes for now. + */ + if (dp->is_edp) + return MODE_OK; + if ((dp->max_pclk_khz <= 0) || (dp->max_pclk_khz > DP_MAX_PIXEL_CLK_KHZ) || (mode->clock > dp->max_pclk_khz))