From patchwork Thu Feb 17 21:36:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuogee Hsieh X-Patchwork-Id: 543741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45085C4332F for ; Thu, 17 Feb 2022 21:36:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229694AbiBQVhA (ORCPT ); Thu, 17 Feb 2022 16:37:00 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:60496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245710AbiBQVg7 (ORCPT ); Thu, 17 Feb 2022 16:36:59 -0500 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 452336D1AB; Thu, 17 Feb 2022 13:36:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645133804; x=1676669804; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=4odJ4cwcWZbiiuldcZ9RBKjoxVRmzcS/F73RDRD+s2A=; b=BQ/yiH17mO+r+0ksw7NeRn0k+cWZH4HtzoJO3ifLfuqQS1T0j8XttBxX Dk9mGboGkeu5zgNbp1gE3h4Y+RfdtsG2rR3QGQu2KLW2VAP1fiXstvjY5 Ynsfs+k5MC7bdyaviu68XBm6FIeyl02Ch8lyzc1TsdNZNG0/c2NR4jglt w=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 17 Feb 2022 13:36:43 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Feb 2022 13:36:42 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Thu, 17 Feb 2022 13:36:42 -0800 Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Thu, 17 Feb 2022 13:36:41 -0800 From: Kuogee Hsieh To: , , , , , , , , , CC: Kuogee Hsieh , , , , , , Subject: [PATCH v8 2/4] drm/msm/dpu: replace BIT(x) with correspond marco define string Date: Thu, 17 Feb 2022 13:36:26 -0800 Message-ID: <1645133788-5057-3-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1645133788-5057-1-git-send-email-quic_khsieh@quicinc.com> References: <1645133788-5057-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org To improve code readability, this patch replace BIT(x) with correspond register bit define string Signed-off-by: Kuogee Hsieh Reviewed-by: Stephen Boyd --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 284f561..c2cd185 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -60,6 +60,12 @@ #define INTF_MUX 0x25C +#define INTF_CFG_ACTIVE_H_EN BIT(29) +#define INTF_CFG_ACTIVE_V_EN BIT(30) + +#define INTF_CFG2_DATABUS_WIDEN BIT(0) +#define INTF_CFG2_DATA_HCTL_EN BIT(4) + static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, const struct dpu_mdss_cfg *m, void __iomem *addr, @@ -130,13 +136,13 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, if (active_h_end) { active_hctl = (active_h_end << 16) | active_h_start; - intf_cfg |= BIT(29); /* ACTIVE_H_ENABLE */ + intf_cfg |= INTF_CFG_ACTIVE_H_EN; } else { active_hctl = 0; } if (active_v_end) - intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */ + intf_cfg |= INTF_CFG_ACTIVE_V_EN; hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; display_hctl = (hsync_end_x << 16) | hsync_start_x; @@ -182,7 +188,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, (0x21 << 8)); if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) { - intf_cfg2 |= BIT(4); + intf_cfg2 |= INTF_CFG2_DATA_HCTL_EN; display_data_hctl = display_hctl; DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2); DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl);