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[5/8] ARM: dts: qcom: sdx65: Add support for A7 PLL clock

Message ID 1644822069-27513-1-git-send-email-quic_rohiagar@quicinc.com
State Accepted
Commit 02c5553523c6cfdab4335ab26ff65f679c7c91ac
Headers show
Series [1/8] dt-bindings: mailbox: Add binding for SDX65 APCS | expand

Commit Message

Rohit Agarwal Feb. 14, 2022, 7:01 a.m. UTC 
On SDX65 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 arch/arm/boot/dts/qcom-sdx65.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 556a2e3..2900ffe 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -125,6 +125,14 @@ 
 			      <0x17802000 0x1000>;
 		};
 
+		a7pll: clock@17808000 {
+			compatible = "qcom,sdx65-a7pll";
+			reg = <0x17808000 0x1000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "bi_tcxo";
+			#clock-cells = <0>;
+		};
+
 		timer@17820000 {
 			#address-cells = <1>;
 			#size-cells = <1>;