From patchwork Thu Dec 2 00:00:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 519872 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB235C433EF for ; Thu, 2 Dec 2021 00:02:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344137AbhLBAFN (ORCPT ); Wed, 1 Dec 2021 19:05:13 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:3936 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353979AbhLBAEX (ORCPT ); Wed, 1 Dec 2021 19:04:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1638403263; x=1669939263; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=JGow5gSyCVGGIvARjpIWCWieeUWr8i3gh6AHITcaPMM=; b=ak9cw5YMd5IuHfCLxosGdMnYb405LnUF61ka1ywtUWH1VIxKgh4AbYv0 35/1foUcZURIX/Pv4CyNUQfqlkK/Vy4C+LLdx2x1wwDeNXOvZ9ztC4+6C boNCmGMvCIFY6puyLhyJcEFvxOjUaUjDr0T7+8eWoGTtF4jzubdoeltyS 8=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 01 Dec 2021 16:01:02 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2021 16:01:02 -0800 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Wed, 1 Dec 2021 16:01:01 -0800 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Wed, 1 Dec 2021 16:00:58 -0800 From: Fenglin Wu To: , , , Andy Gross , Bjorn Andersson , Rob Herring , CC: , , , , Subject: [RESEND PATCH v3 07/10] bindings: spmi: spmi-pmic-arb: mark interrupt properties as optional Date: Thu, 2 Dec 2021 08:00:09 +0800 Message-ID: <1638403212-29265-8-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1638403212-29265-1-git-send-email-quic_fenglinw@quicinc.com> References: <1638403212-29265-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins Mark all interrupt related properties as optional instead of required. Some boards do not required PMIC IRQ support and it isn't needed to handle SPMI bus transactions, so specify it as optional. Signed-off-by: David Collins Signed-off-by: Fenglin Wu Acked-by: Rob Herring --- Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt index ca645e2..6332507 100644 --- a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt +++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt @@ -29,6 +29,8 @@ Required properties: - #size-cells : must be set to 0 - qcom,ee : indicates the active Execution Environment identifier (0-5) - qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5) + +Optional properties: - interrupts : interrupt list for the PMIC Arb controller, must contain a single interrupt entry for the peripheral interrupt - interrupt-names : corresponding interrupt names for the interrupts